Validated ligand binding sites in CCK receptors. Next step: Computer aided design of novel CCK ligands

Computer-aided drug design becomes an important part of G-protein coupled receptors (GPCR) drug discovery process that is applied for improving the efficiency of derivation and optimization of novel ligands. It represents the combination of methods that-use-structural information of a receptor binding site of known ligands to design new ligands. In this report, we give a brief description of ligand binding sites in cholecystokinin and gastrin receptors (CK1R and CCK2R) which were delineated using experimental and computational methods, and then, we show how the validated ligand binding sites can be used to design and improve novel ligands. The translation of the knowledge of ligand-binding sites of different GPCRs to computer-aided design of novel ligands is summarized.

A Sensitivity Approach for Eliminating Clashes from Computer Aided Design Model Assemblies

Clashes occur when components in an assembly unintentionally violate others. If clashes are not identified and designed out before manufacture, product function will be reduced or substantial cost will be incurred in rework. This paper introduces a novel approach for eliminating clashes by identifying which parameters defining the part features in a computer aided design (CAD) assembly need to change and by how much. Sensitivities are calculated for each parameter defining the part and the assembly as the change in clash volume due to a change in each parameter value. These sensitivities give an indication of important parameters and are used to predict the optimum combination of changes in each parameter to eliminate the clash. Consideration is given to the fact that it is sometimes preferable to modify some components in an assembly rather than others and that some components in an assembly cannot be modified as the designer does not have control over their shape. Successful elimination of clashes has been demonstrated in a number of example assemblies.

Time Efficient Assessment and Feedback Methods for Large Computer-Aided-Design Cohorts

Timely and individualized feedback on coursework is desirable from a student perspective as it facilitates formative development and encourages reflective learning practice. Faculty however are faced with a significant and potentially time consuming challenge when teaching larger cohorts if they are to provide feedback which is timely, individualized and detailed. Additionally, for subjects which assess non-traditional submissions, such as Computer-Aided-Design (CAD), the methods for assessment and feedback tend not to be so well developed or optimized. Issues can also arise over the consistency of the feedback provided. Evaluations of Computer-Assisted feedback in other disciplines (Denton et al, 2008), (Croft et al, 2001) have shown students prefer this method of feedback to traditional “red pen” marking and also that such methods can be more time efficient for faculty.
Herein, approaches are described which make use of technology and additional software tools to speed up, simplify and automate assessment and the provision of feedback for large cohorts of first and second year engineering students studying modules where CAD files are submitted electronically. A range of automated methods are described and compared with more “manual” approaches. Specifically one method uses an application programming interface (API) to interrogate SolidWorks models and extract information into an Excel spreadsheet, which is then used to automatically send feedback emails. Another method describes the use of audio recordings made during model interrogation which reduces the amount of time while increasing the level of detail provided as feedback.
Limitations found with these methods and problems encountered are discussed along with a quantified assessment of time saving efficiencies made.

Chip design for high-performance DSP

Advances in silicon technology have been a key development in the realisation of many telecommunication and signal processing systems. In many cases, the development of application-specific digital signal processing (DSP) chips is the most cost-effective solution and provides the highest performance. Advances made in computer-aided design (CAD) tools and design methodologies now allow designers to develop complex chips within months or even weeks. This paper gives an insight into the challenges and design methodologies of implementing advanced highperformance chips for DSP. In particular, the paper reviews some of the techniques used to develop circuit architectures from high-level descriptions and the tools which are then used to realise silicon layout.

Designing computer architecture research workloads

MinneSPEC proposes reduced input sets that microprocessor designers can use to model representative short-running workloads. A four-step methodology verifies the program behavior similarity of these input sets to reference sets.

Design of composite stiffener run-outs for damage tolerance

A major concern in stiffener run-out regions, where the stiffener is terminated due to a cut-out, intersecting rib, or some other structural feature which interrupts the load path, is the relatively weak skin–stiffener interface in the absence of mechanical fasteners. More damage tolerant stiffener run-outs are clearly required and these are investigated in this paper. Using a parametric finite element analysis, the run-out region was optimised for stable debonding crack growth. The modified run-out, as well as a baseline configuration, were manufactured and tested. Damage initiation and propagation was investigated in detail using state-of-the-art monitoring equipment including Acoustic Emission and Digital Image Correlation. As expected, the baseline configuration failed catastrophically. The modified run-out showed improved crack-growth stability, but subsequent delamination failure in the stiffener promptly led to catastrophic failure.

Managing Equivalent Representations of Design and Analysis Models

There is a requirement for better integration between design and analysis tools, which is difficult due to their different objectives, separate data representations and workflows. Currently, substantial effort is required to produce a suitable analysis model from design geometry. Robust links are required between these different representations to enable analysis attributes to be transferred between different design and analysis packages for models at various levels of fidelity.

This paper describes a novel approach for integrating design and analysis models by identifying and managing the relationships between the different representations. Three key technologies, Cellular Modeling, Virtual Topology and Equivalencing, have been employed to achieve effective simulation model management. These technologies and their implementation are discussed in detail. Prototype automated tools are introduced demonstrating how multiple simulation models can be linked and maintained to facilitate seamless integration throughout the design cycle.

Design methodology for low power and arametric robustness through output-quality modulation:Application to color-interpolation filtering

Power dissipation and robustness to process variation have conflicting design requirements. Scaling of voltage is associated with larger variations, while Vdd upscaling or transistor upsizing for parametric-delay variation tolerance can be detrimental for power dissipation. However, for a class of signal-processing systems, effective tradeoff can be achieved between Vdd scaling, variation tolerance, and output quality. In this paper, we develop a novel low-power variation-tolerant algorithm/architecture for color interpolation that allows a graceful degradation in the peak-signal-to-noise ratio (PSNR) under aggressive voltage scaling as well as extreme process variations. This feature is achieved by exploiting the fact that all computations used in interpolating the pixel values do not equally contribute to PSNR improvement. In the presence of Vdd scaling and process variations, the architecture ensures that only the less important computations are affected by delay failures. We also propose a different sliding-window size than the conventional one to improve interpolation performance by a factor of two with negligible overhead. Simulation results show that, even at a scaled voltage of 77% of nominal value, our design provides reasonable image PSNR with 40% power savings. © 2006 IEEE.