Time Efficient Assessment and Feedback Methods for Large Computer-Aided-Design Cohorts

Timely and individualized feedback on coursework is desirable from a student perspective as it facilitates formative development and encourages reflective learning practice. Faculty however are faced with a significant and potentially time consuming challenge when teaching larger cohorts if they are to provide feedback which is timely, individualized and detailed. Additionally, for subjects which assess non-traditional submissions, such as Computer-Aided-Design (CAD), the methods for assessment and feedback tend not to be so well developed or optimized. Issues can also arise over the consistency of the feedback provided. Evaluations of Computer-Assisted feedback in other disciplines (Denton et al, 2008), (Croft et al, 2001) have shown students prefer this method of feedback to traditional “red pen” marking and also that such methods can be more time efficient for faculty.
Herein, approaches are described which make use of technology and additional software tools to speed up, simplify and automate assessment and the provision of feedback for large cohorts of first and second year engineering students studying modules where CAD files are submitted electronically. A range of automated methods are described and compared with more “manual” approaches. Specifically one method uses an application programming interface (API) to interrogate SolidWorks models and extract information into an Excel spreadsheet, which is then used to automatically send feedback emails. Another method describes the use of audio recordings made during model interrogation which reduces the amount of time while increasing the level of detail provided as feedback.
Limitations found with these methods and problems encountered are discussed along with a quantified assessment of time saving efficiencies made.

A Sensitivity Approach for Eliminating Clashes from Computer Aided Design Model Assemblies

Clashes occur when components in an assembly unintentionally violate others. If clashes are not identified and designed out before manufacture, product function will be reduced or substantial cost will be incurred in rework. This paper introduces a novel approach for eliminating clashes by identifying which parameters defining the part features in a computer aided design (CAD) assembly need to change and by how much. Sensitivities are calculated for each parameter defining the part and the assembly as the change in clash volume due to a change in each parameter value. These sensitivities give an indication of important parameters and are used to predict the optimum combination of changes in each parameter to eliminate the clash. Consideration is given to the fact that it is sometimes preferable to modify some components in an assembly rather than others and that some components in an assembly cannot be modified as the designer does not have control over their shape. Successful elimination of clashes has been demonstrated in a number of example assemblies.

Validated ligand binding sites in CCK receptors. Next step: Computer aided design of novel CCK ligands

Computer-aided drug design becomes an important part of G-protein coupled receptors (GPCR) drug discovery process that is applied for improving the efficiency of derivation and optimization of novel ligands. It represents the combination of methods that-use-structural information of a receptor binding site of known ligands to design new ligands. In this report, we give a brief description of ligand binding sites in cholecystokinin and gastrin receptors (CK1R and CCK2R) which were delineated using experimental and computational methods, and then, we show how the validated ligand binding sites can be used to design and improve novel ligands. The translation of the knowledge of ligand-binding sites of different GPCRs to computer-aided design of novel ligands is summarized.

Maintaining a grasp on reality – Is our validation and design effort focused in the same direction?

This article examines the influence on the engineering design process of the primary objective of validation, whether it is proving a model, a technology or a product. Through the examination of a number of stiffened panel case studies, the relationships between simulation, validation, design and the final product are established and discussed. The work demonstrates the complex interactions between the original (or anticipated) design model, the analysis model, the validation activities and the product in service. The outcome shows clearly some unintended consequences. High fidelity validation test simulations require a different set of detailed parameters to accurately capture behaviour. By doing so, there is a divergence from the original computer-aided design model, intrinsically limiting the value of the validation with respect to the product. This work represents a shift from the traditional perspective of encapsulating and controlling errors between simulation and experimental test to consideration of the wider design-test process. Specifically, it is a reflection on the implications of how models are built and validated, and the effect on results and understanding of structural behaviour. This article then identifies key checkpoints in the design process and how these should be used to update the computer-aided design system parameters for a design. This work strikes at a fundamental challenge in understanding the interaction between design, certification and operation of any complex system.

6-T SRAM cell design with nanoscale double-gate SOI MOSFETs: impact of source/drain engineering and circuit topology

The impact of source/drain engineering on the performance of a six-transistor (6-T) static random access memory (SRAM) cell, based on 22 nm double-gate (DG) SOI MOSFETs, has been analyzed using mixed-mode simulation, for three different circuit topologies for low voltage operation. The trade-offs associated with the various conflicting requirements relating to read/write/standby operations have been evaluated comprehensively in terms of eight performance metrics, namely retention noise margin, static noise margin, static voltage/current noise margin, write-ability current, write trip voltage/current and leakage current. Optimal design parameters with gate-underlap architecture have been identified to enhance the overall SRAM performance, and the influence of parasitic source/drain resistance and supply voltage scaling has been investigated. A gate-underlap device designed with a spacer-to-straggle (s/sigma) ratio in the range 2-3 yields improved SRAM performance metrics, regardless of circuit topology. An optimal two word-line double-gate SOI 6-T SRAM cell design exhibits a high SNM similar to 162 mV, I-wr similar to 35 mu A and low I-leak similar to 70 pA at V-DD = 0.6 V, while maintaining SNM similar to 30% V-DD over the supply voltage (V-DD) range of 0.4-0.9 V.

Engineering source/drain extension regions in nanoscale double gate (DG) SOI MOSFETs: Analytical model and design considerations

In this paper, we propose for the first time, an analytical model for short channel effects in nanoscale source/drain extension region engineered double gate (DG) SOI MOSFETs. The impact of (i) lateral source/drain doping gradient (d), (ii) spacer width (s), (iii) spacer to doping gradient ratio (s/d) and (iv) silicon film thickness (T-si), on short channel effects - threshold voltage (V-th) and subthreshold slope (S), on-current (I-on), off-current (I-on) and I-on/I-off is extensively analysed by using the analytical model and 2D device simulations. The results of the analytical model confirm well with simulated data over the entire range of spacer widths, doping gradients and effective channel lengths. Results show that lateral source/drain doping gradient along with spacer width can not only effectively control short channel effects, thus presenting low off-current, but can also be optimised to achieve high values of on-currents. The present work provides valuable design insights in the performance of nanoscale DG Sol devices with optimal source/drain engineering and serves as a tool to optimise important device and technological parameters for 65 nm technology node and below. (c) 2006 Elsevier Ltd. All rights reserved.

Harmonic generation and wave mixing in nonlinear metamaterials and photonic crystals (Invited paper)

The basic concepts and phenomenology of wave mixing and harmonic generation are reviewed in context of the recent advances in the enhanced nonlinear activity in metamaterials and photonic crystals. The effects of dispersion, field confinement and phase synchronism are illustrated by the examples of the on-purpose designed artificial nonlinear structures. (c) 2012 Wiley Periodicals, Inc. Int J RF and Microwave CAE 22:469482, 2012.

Performance projections and design optimization of planar double gate SOI MOSFETs for logic technology applications

In this paper, by investigating the influence of source/drain extension region engineering (also known as gate-source/drain underlap) in nanoscale planar double gate (DG) SOI MOSFETs, we offer new insights into the design of future nanoscale gate-underlap DG devices to achieve ITRS projections for high performance (HP), low standby power (LSTP) and low operating power (LOP) logic technologies. The impact of high-kappa gate dielectric, silicon film thickness, together with parameters associated with the lateral source/drain doping profile, is investigated in detail. The results show that spacer width along with lateral straggle can not only effectively control short-channel effects, thus presenting low off-current in a gate underlap device, but can also be optimized to achieve lower intrinsic delay and higher on-off current ratio (I-on/I-off). Based on the investigation of on-current (I-on), off-current (I-off), I-on/I-off, intrinsic delay (tau), energy delay product and static power dissipation, we present design guidelines to select key device parameters to achieve ITRS projections. Using nominal gate lengths for different technologies, as recommended from ITRS specification, optimally designed gate-underlap DG MOSFETs with a spacer-to-straggle (s/sigma) ratio of 2.3 for HP/LOP and 3.2 for LSTP logic technologies will meet ITRS projection. However, a relatively narrow range of lateral straggle lying between 7 to 8 nm is recommended. A sensitivity analysis of intrinsic delay, on-current and off-current to important parameters allows a comparative analysis of the various design options and shows that gate workfunction appears to be the most crucial parameter in the design of DG devices for all three technologies. The impact of back gate misalignment on I-on, I-off and tau is also investigated for optimized underlap devices.

THEORY AND DESIGN OF A TUNABLE QUASI-LUMPED QUADRATURE COUPLER

In this article, we present the theory and a design methodology for a unable Quasi-Lumped Quadrature Coupler (QLQC). Because of its topology, the coupler is simply reconfigured by switching the bias of two varactor diodes via a very simple DC bias circuitry. No additional capacitors or inductors are required. A prototype at 3.5 GHz is etched on a 0.130-mm-thick layer substrate with a dielectric material of relative permittivity of 2.22. The simulated and measured scattering parameters are, presented. (c) 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 2219-2222 2009: Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24526