Systolic building block for high performance recursive filtering

A novel bit level systolic array is presented that can be used as a building block in the construction of recursive digital filters. The circuit accepts bit-parallel input data, is pipelined at the bit level, and exhibits a very high throughput rate. The most important feature of the circuit is that it allows recursive operations to be implemented directly without incurring the large m cycle latency (where m is approximately the word length) normally associated with such systems. The use of this circuit in the construction of both first- and second-order IIR (infinite-impulse-response) filters is described.

Algorithms and architectures for high performance recursive filtering

Recently, a number of most significant digit (msd) first bit parallel multipliers for recursive filtering have been reported. However, the design approach which has been used has, in general, been heuristic and consequently, optimality has not always been assured. In this paper, msd first multiply accumulate algorithms are described and important relationships governing the dependencies between latency, number representations, etc are derived. A more systematic approach to designing recursive filters is illustrated by applying the algorithms and associated relationships to the design of cascadable modules for high sample rate IIR filtering and wave digital filtering.

Systematic methodology for the design of high performance recursive digital filters

A systematic design methodology is described for the rapid derivation of VLSI architectures for implementing high performance recursive digital filters, particularly ones based on most significant digit (msd) first arithmetic. The method has been derived by undertaking theoretical investigations of msd first multiply-accumulate algorithms and by deriving important relationships governing the dependencies between circuit latency, levels of pipe-lining and the range and number representations of filter operands. The techniques described are general and can be applied to both bit parallel and bit serial circuits, including those based on on-line arithmetic. The method is illustrated by applying it to the design of a number of highly pipelined bit parallel IIR and wave digital filter circuits. It is shown that established architectures, which were previously designed using heuristic techniques, can be derived directly from the equations described.

A 76-84 GHz SiGe power amplifier array employing low-loss four-way differential combining transformer

This paper presents holistic design of a novel four-way differential power-combining transformer for use in millimeter-wave power-amplifier (PA). The combiner with an inner radius of 25 µm exhibits a record low insertion loss of 1.25 dB at 83.5 GHz. It is designed to simultaneously act as a balanced-to-unbalanced converter, removing the need for additional BALUNs typically required in differential circuits. A complete circuit comprised of a power splitter, two-stage differential cascode PA array, a power combiner as well as input and output matching elements was designed and realized in SiGe technology with f/f 170/250 GHz. Measured small-signal gain of at least 16.8 dB was obtained from 76.4 to 85.3 GHz with a peak 19.5 dB at 83 GHz. The prototype delivered 12.5 dBm output referred 1 dB compression point and 14 dBm saturated output power when operated from a 3.2 V dc supply voltage at 78 GHz.

Nanoscale Origins of Nonlinear Behavior in Ferroic Thin Films

The nonlinear response of a ferroic to an applied field has been studied through the phenomenological Rayleigh Law for over a hundred years. Yet, despite this, the fundamental physical mechanisms at the nanoscale that lead to macroscopic Rayleigh behavior have remained largely elusive, and experimental evidence at small length scales is limited. Here, it is shown using a combination of scanning probe techniques and phase field modeling, that nanoscale piezoelectric response in prototypical Pb(Zr,Ti)O3 films appears to follow a distinctly non-Rayleigh regime. Through statistical analysis, it is found that an averaging of local responses can lead directly to Rayleigh-like behavior of the strain on a macroscale. Phase-field modeling confirms the twist of the ferroelastic interface is key in enhancing piezoelectric response. The studies shed light on the nanoscale origins of nonlinear behavior in disordered ferroics.

Nonlinear phenomena in multiferroic nanocapacitors:joule heating and electromechanical effects

We demonstrate an approach for probing nonlinear electromechanical responses in BiFeO(3) thin film nanocapacitors using half-harmonic band excitation piezoresponse force microscopy (PFM). Nonlinear PFM images of nanocapacitor arrays show clearly visible clusters of capacitors associated with variations of local leakage current through the BiFeO(3) film. Strain spectroscopy measurements and finite element modeling point to significance of the Joule heating and show that the thermal effects caused by the Joule heating can provide nontrivial contributions to the nonlinear electromechanical responses in ferroic nanostructures. This approach can be further extended to unambiguous mapping of electrostatic signal contributions to PFM and related techniques.

Nonlinear dust-acoustic solitary waves in strongly coupled dusty plasmas

Dust-acoustic waves are investigated in a three-component plasma consisting of strongly coupled dust particles and Maxwellian electrons and ions. A fluid model approach is used, with the effects of strong coupling being accounted for by an effective electrostatic "pressure" which is a function of the dust number density and the electrostatic potential. Both linear and weakly nonlinear cases are considered by derivation and analysis of the linear dispersion relation and the Korteweg-de Vries equation, respectively. In contrast to previous studies using this model, this paper presents the results arising from an expansion of the dynamical form of the electrostatic pressure, accounting for the variations in its value in the vicinity of the wave. DOI: 10.1103/PhysRevE.86.066404

A Unified Scheduler for Recursive and Task Dataflow Parallelism

Task dataflow languages simplify the specification of parallel programs by dynamically detecting and enforcing dependencies between tasks. These languages are, however, often restricted to a single level of parallelism. This language design is reflected in the runtime system, where a master thread explicitly generates a task graph and worker threads execute ready tasks and wake-up their dependents. Such an approach is incompatible with state-of-the-art schedulers such as the Cilk scheduler, that minimize the creation of idle tasks (work-first principle) and place all task creation and scheduling off the critical path. This paper proposes an extension to the Cilk scheduler in order to reconcile task dependencies with the work-first principle. We discuss the impact of task dependencies on the properties of the Cilk scheduler. Furthermore, we propose a low-overhead ticket-based technique for dependency tracking and enforcement at the object level. Our scheduler also supports renaming of objects in order to increase task-level parallelism. Renaming is implemented using versioned objects, a new type of hyper object. Experimental evaluation shows that the unified scheduler is as efficient as the Cilk scheduler when tasks have no dependencies. Moreover, the unified scheduler is more efficient than SMPSS, a particular implementation of a task dataflow language.