Service user involvement in drug treatment programs: Barriers to implementation and potential benefits for client recovery

Service user forums have the potential for improving awareness of services, empowering service users and strengthening community partnerships within an inclusive treatment and rehabilitation framework. The research aimed to investigate perspectives about service user involvement in order to inform the development of effective service user forum(s) in west Ireland. A total of 30 interviews with key service providers and 12 interviews with service users were conducted, with interview questions focusing on: (1) awareness of the Service User Support Team and (2) barriers to service user involvement and the development of service user forums in the region. An integrated data collection and thematic analysis was undertaken. Current levels of service user involvement were low, restricted by one-way communication and appeared grounded in user-provider power differentials and stigma relating to drug dependency. Service providers queried the actual terms of reference, capacity and training that would be needed for service user forums to advocate and lobby for service users. The use of existing support groups, creation of internet user forums and rotation of rural meetings were recommended to promote engagement among service users. The research underscores the need for transparency, resources and a framework for good practice that reflects a participatory approach


Read More: http://informahealthcare.com/doi/abs/10.3109/09687637.2012.671860

IMPLEMENTATION OF SIGNAL PROCESSING FUNCTIONS USING 1-BIT SYSTOLIC ARRAYS.

The use of systolic arrays of 1-bit cells to implement a range of important signal processing functions is demonstrated. Two examples, a pipelined multiplier and a pipelined bit-slice transform circuit, are given. This approach has many important implications for silicon technology, and these are outlined.

Bit-level systolic array implementation of the Winograd Fourier transform algorithm

A bit level systolic array system is proposed for the Winograd Fourier transform algorithm. The design uses bit-serial arithmetic and, in common with other systolic arrays, features nearest-neighbor interconnections, regularity and high throughput. The short interconnections in this method contrast favorably with the long interconnections between butterflies required in the FFT. The structure is well suited to VLSI implementations. It is demonstrated how long transforms can be implemented with components designed to perform a short length transform. These components build into longer transforms preserving the regularity and structure of the short length transform design.

SYSTOLIC IMPLEMENTATION OF THE WINOGRAD FOURIER TRANSFORM ALGORITHM.

A bit-level systolic array system is proposed for the Winograd Fourier transform algorithm. The design uses bit-serial arithmetic and, in common with other systolic arrays, features nearest neighbor interconnections, regularity, and high throughput. The short interconnections in this method contrast favorably with the long interconnections between butterflies required in the FFT. The structure is well suited to VLSI implementations. It is demonstrated how long transforms can be implemented with components designed to perform short-length transforms. These components build into longer transforms, preserving the regularity and structure of the short-length transform design.

HIGH SPEED CMOS/SOS IMPLEMENTATION OF A BIT LEVEL SYSTOLIC CORRELATOR.

The fabrication and performance of the first bit-level systolic correlator array is described. The application of systolic array concepts at the bit level provides a simple and extremely powerful method for implementing high-performance digital processing functions. The resulting structure is highly regular, facilitating yield enhancement through fault-tolerant redundancy techniques and therefore ideally suited to implementation as a VLSI chip. The CMOS/SOS chip operates at 35 MHz, is fully cascadable and exhibits 64-stage correlation for 1-bit reference and 4-bit data. 7 refs.

Design and implementation of the symmetrically extended 2-D wavelet transform

The inclusion of the Discrete Wavelet Transform in the JPEG-2000 standard has added impetus to the research of hardware architectures for the two-dimensional wavelet transform. In this paper, a VLSI architecture for performing the symmetrically extended two-dimensional transform is presented. This architecture conforms to the JPEG-2000 standard and is capable of near-optimal performance when dealing with the image boundaries. The architecture also achieves efficient processor utilization. Implementation results based on a Xilinx Virtex-2 FPGA device are included.

High-performance FPGA implementation of DES using a novel method for implementing the key schedule

A generic, parameterisable key scheduling core is presented, which can be utilised in pipelinable private-key encryption algorithms. The data encryption standard (DES) algorithm, which lends itself readily to pipelining, is utilised to exemplify this novel key scheduling method and the broader applicability of the method to other encryption algorithms is illustrated. The DES design is implemented on Xilinx Virtex FPGA technology. Utilising the novel method, a 16-stage pipelined DES design is achieved, which can run at an encryption rate of 3.87 Gbit/s. This result is among the fastest hardware implementations and is a factor 28 times faster than software implementations.

CMOS IMPLEMENTATION OF A SYSTOLIC MULTI-BIT CONVOLVER CHIP.

The implementation of a multi-bit convolver chip based on a systolic array is described. The convolver is fabricated on a 7mm multiplied by 8mm CMOS chip and operates on 8-bit serial data and coefficient words. It has a length of 17 stages, and this is cascadable. The circuit can be clocked at more than 20 MHz giving a data throughput rate of greater than 1 Mword/s. Details of important implementation decisions and a summary of chip characteristics are given together with the advantages which the systolic approach has afforded to the design process.

Was It Something I Ate? Implementation of the FDA Seafood HACCP Program

We develop a theoretical model of enforcement and compliance under HACCP regulation and use the FDA's seafood inspection records to examine: (1) if the FDA has targeted its inspections under HACCP regulation; (2) the effects of inspections on compliance with HACCP and plant sanitation standards; and (3) the relationship between compliance with HACCP and preexisting sanitation standards. There is some evidence of targeting based on product risk, but not on past compliance performance. The threat of an inspection increases the likelihood of compliance, but only for sanitation inspections, not for HACCP. HACCP compliance does not improve compliance with sanitation standards. © 2008 American Agricultural Economics Association.

Numerical analysis of intralaminar failure mechanisms in composite structures, Part I: FE implementation

This paper presents a three-dimensional continuum damage mechanics-based material model which was implemented in an implicit finite element code to simulate the progressive intralaminar degradation of fibre reinforced laminates. The damage model is based on ply failure mechanisms and uses seven damage variables assigned to tensile, compressive and shear damage at a ply level. Non-linear behaviour and irreversibility were taken into account and modelled. Some issues on the numerical implementation of the damage model are discussed and solutions proposed. Applications of the methodology are presented in Part II

Implementation and testing of Lanczos-based algorithms for Random-Phase Approximation eigenproblems

The treatment of the Random-Phase Approximation Hamiltonians, encountered in different frameworks, like time-dependent density functional theory or Bethe-Salpeter equation, is complicated by their non-Hermicity. Compared to their Hermitian Hamiltonian counterparts, computational methods for the treatment of non-Hermitian Hamiltonians are often less efficient and less stable, sometimes leading to the breakdown of the method. Recently [Gruning et al. Nano Lett. 8 (2009) 28201, we have identified that such Hamiltonians are usually pseudo-Hermitian. Exploiting this property, we have implemented an algorithm of the Lanczos type for Random-Phase Approximation Hamiltonians that benefits from the same stability and computational load as its Hermitian counterpart, and applied it to the study of the optical response of carbon nanotubes. We present here the related theoretical grounds and technical details, and study the performance of the algorithm for the calculation of the optical absorption of a molecule within the Bethe-Salpeter equation framework. (C) 2011 Elsevier B.V. All rights reserved.