Monitoring the performance of aerodrome ground lighting

This article provides an overview of a novel prototype device that can be used to aid airports in monitoring their landing lighting. Known as Aerodrome Ground Lighting (AGL), the device is comprised of a camera that is capable of capturing images of landing lighting as aircraft approach the airport. AGL is designed to automatically examine landing lighting to assess if it is operating under uniform brightness standards (i.e., luminous intensity of luminares) that aviation governing bodies require. A detailed discussion of the hardware and software requirements of AGL -- currently under joint development by researchers at Queens University Belfast and Cobham Flight Inspection Limited -- is presented. Results from the research indicate that assessing the performance of both ground-based runway luminaries and elevated approach luminaries is possible, though further testing is needed for full validation.

High performance IP lookup circuit using DDR SDRAM

DDR-SDRAM based data lookup techniques are evolving into a core technology for packet lookup applications for data network, benefitting from the features of high density, high bandwidth and low price of DDR memory products in the market. Our proposed DDR-SDRAM based lookup circuit is capable of achieving IP header lookup for network line-rates of up to 10Gbps, providing a solution on high-performance and economic packet header inspections. ©2008 IEEE.

Systolic building block for high performance recursive filtering

A novel bit level systolic array is presented that can be used as a building block in the construction of recursive digital filters. The circuit accepts bit-parallel input data, is pipelined at the bit level, and exhibits a very high throughput rate. The most important feature of the circuit is that it allows recursive operations to be implemented directly without incurring the large m cycle latency (where m is approximately the word length) normally associated with such systems. The use of this circuit in the construction of both first- and second-order IIR (infinite-impulse-response) filters is described.

Algorithms and architectures for high performance recursive filtering

Recently, a number of most significant digit (msd) first bit parallel multipliers for recursive filtering have been reported. However, the design approach which has been used has, in general, been heuristic and consequently, optimality has not always been assured. In this paper, msd first multiply accumulate algorithms are described and important relationships governing the dependencies between latency, number representations, etc are derived. A more systematic approach to designing recursive filters is illustrated by applying the algorithms and associated relationships to the design of cascadable modules for high sample rate IIR filtering and wave digital filtering.

Bit-level systolic architecture for very high performance IIR filters

A novel bit-level systolic array architecture for implementing bit-parallel IIR filter sections is presented. The authors have shown previously how the fundamental obstacle of pipeline latency in recursive structures can be overcome by the use of redundant arithmetic in combination with bit-level feedback. These ideas are extended by optimizing the degree of redundancy used in different parts of the circuit and combining redundant circuit techniques with those of conventional arithmetic. The resultant architecture offers significant improvements in hardware complexity and throughput rate.

INDEPENDENT EVALUATION OF THE PERFORMANCE OF THE CCITT G. 722 WIDEBAND CODING RECOMMENDATION.

The subjective performance of the G. 722 7-kHz wideband speech coding recommendation using music signals is described. A number of audible distortions specific to music signals were found to be present in real-time evaluations of the coder. As a result, three modifications are proposed which are found to improve the performance for music signals. These modifications are compatible with the G. 722 system configuration. Modifications made to G. 722 to alleviate the most serious aspects of the noise modulation are described: (1) an adaptive bit allocation scheme is used to reduce short and long-term nonoptimality; (2) spectral noise shaping is incorporated, significantly enhancing the subjective performance of certain modes; and (3) backward block adaptive prediction is used.

INDEPENDENT EVALUATION OF THE PERFORMANCE OF THE CCITT G. 722 WIDEBAND CODING RECOMMENDATION USING MUSIC SIGNALS.

The subjective performance of the G. 722 7-kHz wideband speech-coding recommendation using music signals is described. A number of audible distortions specific to music signals were found to be present in real-time evaluations of the coder. As a result, three modifications are proposed which are found to improve the performance for music signals. These modifications are compatible with the G. 722 system configuration. The results obtained clearly demonstrate the very high coding efficiency of subband ADPCM (adaptive differential pulse-code modulation) with comparison to digitally companding and ADM schemes when applied to music signals.

VLSI processor for high-performance arithmetic computations

A high performance VLSI architecture to perform combined multiply-accumulate, divide, and square root operations is proposed. The circuit is highly regular, requires only minimal control, and can be pipelined right down to the bit level. The system can also be reconfigured on every cycle to perform one or more of these operations. The throughput rate for each operation is the same and is wordlength independent. This is achieved using redundant arithmetic. With current CMOS technology, throughput rates in excess of 80 million operations per second are expected.