High Speed FPGA-based implementations of Delayed-LMS filters

A variation of the least means squares (LMS) algorithm, called the delayed LMS (DLMS) algorithm is an ideally suited to achieve highly pipelined, adaptive digital filter implementations. The paper presents an efficient method of determining the delays in the DLMS filter and then transferring these delays using retiming in order to achieve fully pipelined circuit architectures for FPGA implementation. The method has been used to derive a series of retimed delayed LMS (RDLMS) architectures, which considerable reduce the number of delays and convergence time and give superior performance in terms of throughput rate when compared to previous work. Three circuit architectures and three hardware shared versions are presented which have been implemented using the Virtex-II FPGA technology resulting in a throughout rate of 182 Msample/s.

WEBCOM-G: A candidate middleware for Grid-Ireland

WebCom-G is a fledgling Grid Operating System, designed to provide independent service access through interoperability with existing middlewares. It offers an expressive programming model that automatically handles task synchronisation – load balancing, fault tolerance, and task allocation are handled at the WebCom-G system level – without burdening the application writer. These characteristics, together with the ability of its computing model to mix evaluation strategies to match the characteristics of the geographically dispersed facilities and the overall problem- solving environment, make WebCom-G a promising grid middleware candidate.

Virtex FPGA Implementation of a Pipelined Adaptive LMS Predictor for Electronic Support Measures Receivers

High-speed field-programmable gate array (FPGA) implementations of an adaptive least mean square (LMS) filter with application in an electronic support measures (ESM) digital receiver, are presented. They employ "fine-grained" pipelining, i.e., pipelining within the processor and result in an increased output latency when used in the LMS recursive system. Therefore, the major challenge is to maintain a low latency output whilst increasing the pipeline stage in the filter for higher speeds. Using the delayed LMS (DLMS) algorithm, fine-grained pipelined FPGA implementations using both the direct form (DF) and the transposed form (TF) are considered and compared. It is shown that the direct form LMS filter utilizes the FPGA resources more efficiently thereby allowing a 120 MHz sampling rate.

Plasma power measurement and hysteresis in the E-H transition of a rf inductively coupled plasma system

An experimental investigation of the argon plasma behavior near the E-H transition in an inductively coupled Gaseous Electronics Conference reference cell is reported. Electron density and temperature, ion density, argon metastable density, and optical emission measurements have been made as function of input power and gas pressure. When plotted versus plasma power, applied power corrected for coil and hardware losses, no hysteresis is observed in the measured plasma parameter dependence at the E-H mode transition. This suggests that hysteresis in the E-H mode transition is due to ignoring inherent power loss, primarily in the matching system.

FPGA-based minutia matching for biometric fingerprint image database retrieval

In this paper, a parallel-matching processor architecture with early jump-out (EJO) control is proposed to carry out high-speed biometric fingerprint database retrieval. The processor performs the fingerprint retrieval by using minutia point matching. An EJO method is applied to the proposed architecture to speed up the large database retrieval. The processor is implemented on a Xilinx Virtex-E, and occupies 6,825 slices and runs at up to 65 MHz. The software/hardware co-simulation benchmark with a database of 10,000 fingerprints verifies that the matching speed can achieve the rate of up to 1.22 million fingerprints per second. EJO results in about a 22% gain in computing efficiency.

The design of a navigation guidance and control system for an unmanned surface vehicle for environmental monitoring

Maintaining the ecosystem is one of the main concerns in this modern age. With the fear of ever-increasing global warming, the UK is one of the key players to participate actively in taking measures to slow down at least its phenomenal rate. As an ingredient to this process, the Springer vehicle was designed and developed for environmental monitoring and pollutant tracking. This special issue paper highlighted the Springer hardware and software architecture including various navigational sensors, a speed controller, and an environmental monitoring unit. In addition, details regarding the modelling of the vessel were outlined based mainly on experimental data. The formulation of a fault tolerant multi-sensor data fusion technique was also presented. Moreover, control strategy based on a linear quadratic Gaussian controller was developed and simulated on the Springer model.
Gaussian controller is developed and simulated on the Springer model.

Using signed digit arithmetic for low-power multiplication

Hardware implementations of arithmetic operators using signed digit arithmetic have lost some of their earlier popularity. However, SD is revisited and used to realise an efficient radix-16 generic multiplier, which has particular potential for low-power implementation. The SD multiplier algorithm reduces the number of partial products to as much as 1/4, and in initial tests reduces the estimated power consumption to only about 50% of that of the Booth multiplier. It is different from other previous high-radix methods in that it employs a novel method to generate its partial products with zero arithmetic logic.

Reconfigurable video Motion Estimation processor

In this paper, a new reconfigurable multi-standard Motion Estimation (ME) architecture is proposed and a standard-cell based design study is presented. The architecture exhibits simpler control, high throughput and relative low hardware cost and is highly competitive when compared with existing designs for specific video standards. ©2007 IEEE.

Special issue on design and programming of signal processors for multimedia communication:Special issue on design and programming of signal processors for multimedia communication

The technical challenges in the design and programming of signal processors for multimedia communication are discussed. The development of terminal equipment to meet such demand presents a significant technical challenge, considering that it is highly desirable that the equipment be cost effective, power efficient, versatile, and extensible for future upgrades. The main challenges in the design and programming of signal processors for multimedia communication are, general-purpose signal processor design, application-specific signal processor design, operating systems and programming support and application programming. The size of FFT is programmable so that it can be used for various OFDM-based communication systems, such as digital audio broadcasting (DAB), digital video broadcasting-terrestrial (DVB-T) and digital video broadcasting-handheld (DVB-H). The clustered architecture design and distributed ping-pong register files in the PAC DSP raise new challenges of code generation.