Vaginal temperature sensing using UHF radio telemetry

User induced errors are common when women repetitively employ conventional probe type thermometers to chart their basal body temperatures in an effort to indicate ovulation. An alternative technique employing a two-part telemetric thermometer is proposed, with low-power, SAWR-controlled UHF radio as the transmission medium. Worn overnight in the vagina, the 1 mu W erp telemetry transmitter sends pulse modulated data continuously to a microcontroller in a nearby receiver; a real time clock enables programmable sampling and storage of the subject's temperature to 0.1 degrees C resolution. Initial clinical results indicate an enhanced performance compared to oral and axillary temperature trends taken by a mercury-in-glass thermometer. Polar plots of both the isolated and body-worn telemetry transmitte are presented; body indced attenuations of up to 30 dB were measured.

A chiton without a foot

The palaeoloricate ‘polyplacophorans’ are an extinct paraphyletic group of basal chiton-like organisms known primarily from their fossilized valves. Their phylo- genetic placement remains contentious, but they are likely to include both stem-group Polyplacophora and stem- group Aplacophora. Candidates for the latter position include ‘Helminthochiton’ thraivensis from the Ordovician of Scotland, which we redescribe here through a combined optical and micro-CT (XMT) restudy of the type material. The 11 specimens in the type series are all articulated, presenting partial or complete valve series as well as moul- dic preservation of the girdle armature; they demonstrate a vermiform body plan. The valves are typically palaeolori- cate in aspect, but differ in detail from all existing palaeol- oricate genera; we hence erect Phthipodochiton gen. nov. to contain the species. The most notable feature of the fossils is the spicular girdle; this is impersistently preserved, but demonstrably wraps entirely around the ventral surface of the animal, implying that a ‘true’ (i.e. polyplacophoran like) foot was absent, although we do not exclude the pos- sibility of a narrow solenogastre-like median pedal groove having been present. Phthipodochiton thraivensis presents an apparent mosaic of aplacophoran and polyplacophoran features and as such will inform our understanding of the relationship between these groups of extant molluscs. An inference may also be drawn that at least some other pal- aeoloricates possessed an ‘armoured aplacophoran’ body plan, in contrast to the ‘limpet-like’ body plan of extant Polyplacophora.

Generation and control of ultrafast pulse trains for quasi-phase-matching high-harmonic generation

Two techniques are demonstrated to produce ultrashort pulse trains capable of quasi-phase-matching high-harmonic generation. The first technique makes use of an array of birefringent crystals and is shown to generate high-contrast pulse trains with constant pulse spacing. The second technique employs a grating-pair stretcher, a multiple-order wave plate, and a linear polarizer. Trains of up to 100 pulses are demonstrated with this technique, with almost constant inter-pulse separation. It is shown that arbitrary pulse separation can be achieved by introducing the appropriate dispersion. This principle is demonstrated by using an acousto-optic programmable dispersive filter to introduce third-and fourth-order dispersions leading to a linear and quadratic variation of the separation of pulses through the train. Chirped-pulse trains of this type may be used to quasi-phase-match high-harmonic generation in situations where the coherence length varies through the medium. (C) 2010 Optical Society of America

Simple technique for generating trains of ultrashort pulses

A simple method for generating trains of high-contrast femtosecond pulses is proposed and demonstrated: a linearly polarized, frequency-chirped laser pulse is passed through a multiple-order wave plate and a linear polarizer. It is shown theoretically that this arrangement forms a train of laser pulses, and in experiments the production of a train of approximately 100 pulses, each of 200 fs duration, is demonstrated. In combination with an acousto-optic programmable dispersive filter this technique could be used to generate and control pulse trains with chirped spacing. Pulse trains of this type have widespread applications in ultrafast optics. (C) 2007 Optical Society of America.

FPGA Implementations of the Round Two SHA-3 Candidates

The second round of the NIST-run public competition is underway to find a new hash algorithm(s) for inclusion in the NIST Secure Hash Standard (SHA-3). This paper presents the full implementations of all of the second round candidates in hardware with all of their variants. In order to determine their computational efficiency, an important aspect in NIST's round two evaluation criteria, this paper gives an area/speed comparison of each design both with and without a hardware interface, thereby giving an overall impression of their performance in resource constrained and resource abundant environments. The implementation results are provided for a Virtex-5 FPGA device. The efficiency of the architectures for the hash functions are compared in terms of throughput per unit area. To the best of the authors' knowledge, this is the first work to date to present hardware designs which test for all message digest sizes (224, 256, 384, 512), and also the only work to include the padding as part of the hardware for the SHA-3 hash functions.

Software-defined sphere decoding for FPGA-based MIMO detection

Sphere Decoding (SD) is a highly effective detection technique for Multiple-Input Multiple-Output (MIMO) wireless communications receivers, offering quasi-optimal accuracy with relatively low computational complexity as compared to the ideal ML detector. Despite this, the computational demands of even low-complexity SD variants, such as Fixed Complexity SD (FSD), remains such that implementation on modern software-defined network equipment is a highly challenging process, and indeed real-time solutions for MIMO systems such as 4 4 16-QAM 802.11n are unreported. This paper overcomes this barrier. By exploiting large-scale networks of fine-grained softwareprogrammable processors on Field Programmable Gate Array (FPGA), a series of unique SD implementations are presented, culminating in the only single-chip, real-time quasi-optimal SD for 44 16-QAM 802.11n MIMO. Furthermore, it demonstrates that the high performance software-defined architectures which enable these implementations exhibit cost comparable to dedicated circuit architectures.

Rapid Implementation and Optimisation of DSP Systems on SoPC Heterogeneous Platforms

The emergence of programmable logic devices as processing platforms for digital signal processing applications poses challenges concerning rapid implementation and high level optimization of algorithms on these platforms. This paper describes Abhainn, a rapid implementation methodology and toolsuite for translating an algorithmic expression of the system to a working implementation on a heterogeneous multiprocessor/field programmable gate array platform, or a standalone system on programmable chip solution. Two particular focuses for Abhainn are the automated but configurable realisation of inter-processor communuication fabrics, and the establishment of novel dedicated hardware component design methodologies allowing algorithm level transformation for system optimization. This paper outlines the approaches employed in both these particular instances.

Core-based Methodology: An Automated Approach for Implementing a Complete System From Algorithms to a Heterogeneous Network Including FPGAs

In this paper, we present a methodology for implementing a complete Digital Signal Processing (DSP) system onto a heterogeneous network including Field Programmable Gate Arrays (FPGAs) automatically. The methodology aims to allow design refinement and real time verification at the system level. The DSP application is constructed in the form of a Data Flow Graph (DFG) which provides an entry point to the methodology. The netlist for parts that are mapped onto the FPGA(s) together with the corresponding software and hardware Application Protocol Interface (API) are also generated. Using a set of case studies, we demonstrate that the design and development time can be significantly reduced using the methodology developed.

FPGA based Soft-core SIMD Processing: A MIMO-OFDM Fixed-Complexity Sphere Decoder Case Study

To enable reliable data transfer in next generation Multiple-Input Multiple-Output (MIMO) communication systems, terminals must be able to react to fluctuating channel conditions by having flexible modulation schemes and antenna configurations. This creates a challenging real-time implementation problem: to provide the high performance required of cutting edge MIMO standards, such as 802.11n, with the flexibility for this behavioural variability. FPGA softcore processors offer a solution to this problem, and in this paper we show how heterogeneous SISD/SIMD/MIMD architectures can enable programmable multicore architectures on FPGA with similar performance and cost as traditional dedicated circuit-based architectures. When applied to a 4×4 16-QAM Fixed-Complexity Sphere Decoder (FSD) detector we present the first soft-processor based solution for real-time 802.11n MIMO.

From bit level systolic arrays to HDTV processor chips

The initial part of this paper reviews the early challenges (c 1980) in achieving real-time silicon implementations of DSP computations. In particular, it discusses research on application specific architectures, including bit level systolic circuits that led to important advances in achieving the DSP performance levels then required. These were many orders of magnitude greater than those achievable using programmable (including early DSP) processors, and were demonstrated through the design of commercial digital correlator and digital filter chips. As is discussed, an important challenge was the application of these concepts to recursive computations as occur, for example, in Infinite Impulse Response (IIR) filters. An important breakthrough was to show how fine grained pipelining can be used if arithmetic is performed most significant bit (msb) first. This can be achieved using redundant number systems, including carry-save arithmetic. This research and its practical benefits were again demonstrated through a number of novel IIR filter chip designs which at the time, exhibited performance much greater than previous solutions. The architectural insights gained coupled with the regular nature of many DSP and video processing computations also provided the foundation for new methods for the rapid design and synthesis of complex DSP System-on-Chip (SoC), Intellectual Property (IP) cores. This included the creation of a wide portfolio of commercial SoC video compression cores (MPEG2, MPEG4, H.264) for very high performance applications ranging from cell phones to High Definition TV (HDTV). The work provided the foundation for systematic methodologies, tools and design flows including high-level design optimizations based on "algorithmic engineering" and also led to the creation of the Abhainn tool environment for the design of complex heterogeneous DSP platforms comprising processors and multiple FPGAs. The paper concludes with a discussion of the problems faced by designers in developing complex DSP systems using current SoC technology. © 2007 Springer Science+Business Media, LLC.