Common input to different regions of biceps brachii long head

The purpose of the experiment was to compare the level of synchronization exhibited by pairs of motor units located within and between functionally distinct regions of the biceps brachii muscle. Pairs of single motor units were recorded from seven subjects using separate electrodes located in the lateral and medial aspects of the long head of biceps brachii. Participants were required to exert a combination of flexion and supination torques so that both motor units discharged at approximately 10 pps for a parts per thousand yen200 s and the level of motor unit synchronization could be quantified. When motor unit recordings were sufficiently stable at the completion of this synchrony task, a series of ramp contractions with multiple combinations of flexion and supination torques were performed to characterize the recruitment thresholds of the motor units. Common input strength (CIS) was significantly greater (P <0.01) for the within-region pairs of motor units (0.28 extra sync. imps/s, n = 26) than for the between-region pairs (0.13 extra sync. imps/s, n = 18), but did not differ significantly for the 12 within-region pairs from the lateral head and 14 from the medial head (0.27 vs. 0.29 extra sync. imps/s; P = 0.83). Recruitment thresholds were measured for 33 motor units, but there was only a weak association between CIS and the respective recruitment patterns for motor unit pairs (n = 9). The present investigation provides evidence of a differential distribution of synaptic input across the biceps brachii motor neuron pool, but this appears to have minimal association with the recruitment patterns for individual motor units.

Hierarchical synthesis of complex DSP functions on FPGAs

SoC systems are now being increasingly constructed using a hierarchy of subsystems or silicon Intellectual Property (IP) cores. The key challenge is to use these cores in a highly efficient manner which can be difficult as the internal core structure may not be known. A design methodology based on synthesizing hierarchical circuit descriptions is presented. The paper employs the MARS synthesis scheduling algorithm within the existing IRIS synthesis flow and details how it can be enhanced to allow for design exploration of IP cores. It is shown that by accessing parameterised expressions for the datapath latencies in the cores, highly efficient FPGA solutions can be achieved. Hardware sharing at both the hierarchical and flattened levels is explored for a normalized lattice filter and results are presented.

Linear QR architecture for a single chip adaptive beamformer

This paper presents the design of a novel single chip adaptive beamformer capable of performing 50 Gflops, (Giga-floating-point operations/second). The core processor is a QR array implemented on a fully efficient linear systolic architecture, derived using a mapping that allows individual processors for boundary and internal cell operations. In addition, the paper highlights a number of rapid design techniques that have been used to realise this system. These include an architecture synthesis tool for quickly developing the circuit architecture and the utilisation of a library of parameterisable silicon intellectual property (IP) cores, to rapidly develop detailed silicon designs.

A programmable architecture for layered multimedia streams in IPv6 networks

A new configurable architecture is presented that offers multiple levels of video playback by accommodating variable levels of network utilization and bandwidth. By utilizing scalable MPEG-4 encoding at the network edge and using specific video delivery protocols, media streaming components are merged to fully optimize video playback for IPv6 networks, thus improving QoS. This is achieved by introducing “programmable network functionality” (PNF) which splits layered video transmission and distributes it evenly over available bandwidth, reducing packet loss and delay caused by out-of-profile DiffServ classes. An FPGA design is given which gives improved performance, e.g. link utilization, end-to-end delay, and that during congestion, improves on-time delivery of video frames by up to 80% when compared to current “static” DiffServ.

Language and Power: A Resource Book for Students

Language and Power offers a comprehensive survey of the ways in which language intersects and connects with the social, cultural and political aspects of power; provides a comprehensive introduction to the history of the field, and covers all the major approaches, theoretical concepts and methods of analysis in this important and developing area of academic study; covers all the 'traditional' topics, such as race, gender and institutional power, but also incorporates newer material from forensic discourse analysis, the discourse of new capitalism and the study of humour as power; includes readings from works by seminal figures in the field, such as Roger Fowler, Deborah Cameron and Teun van Dijk; uses real texts and examples throughout, including advertisements from cosmetics companies; newspaper articles and headlines; websites and internet media; and spoken dialogues such as a transcription from the Obama and McCain presidential debate; and is accompanied by a supporting website that aims to challenge students at a more advanced level and features a complete four-unit chapter which includes activities, a reading and suggestions for further work.

A Scalable and Programmable Modular Traffic Manager Architecture

A key issue in the design of next generation Internet routers and switches will be provision of traffic manager (TM) functionality in the datapaths of their high speed switching fabrics. A new architecture that allows dynamic deployment of different TM functions is presented. By considering the processing requirements of operations such as policing and congestion, queuing, shaping and scheduling, a solution has been derived that is scalable with a consistent programmable interface. Programmability is achieved using a function computation unit which determines the action (e.g. drop, queue, remark, forward) based on the packet attribute information and a memory storage part. Results of a Xilinx Virtex-5 FPGA reference design are presented.

Power Efficient Dynamic-Range Utilisation for DSP On FPGA

A power and resource efficient ‘dynamic-range utilisation’ technique to increase operational capacity of DSP IP cores by exploiting redundancy in the data epresentation of sampled analogue input data, is presented. By cleverly partitioning dynamic-range into separable processing threads, several data streams are computed concurrently on the same hardware. Unlike existing techniques which act solely to reduce power consumption due to sign extension, here the dynamic range is exploited to increase operational capacity while still achieving reduced power consumption. This extends an existing system-level, power efficient framework for the design of low power DSP IP cores, which when applied to the design of an FFT IP core in a digital receiver system gives an architecture requiring 50% fewer multipliers, 12% fewer slices and 51%-56% less power.