A Scalable and Programmable Modular Traffic Manager Architecture
Data(s) |
01/05/2011
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Resumo |
A key issue in the design of next generation Internet routers and switches will be provision of traffic manager (TM) functionality in the datapaths of their high speed switching fabrics. A new architecture that allows dynamic deployment of different TM functions is presented. By considering the processing requirements of operations such as policing and congestion, queuing, shaping and scheduling, a solution has been derived that is scalable with a consistent programmable interface. Programmability is achieved using a function computation unit which determines the action (e.g. drop, queue, remark, forward) based on the packet attribute information and a memory storage part. Results of a Xilinx Virtex-5 FPGA reference design are presented. |
Identificador |
http://dx.doi.org/10.1145/1968502.1968505 http://www.scopus.com/inward/record.url?scp=84861327928&partnerID=8YFLogxK |
Idioma(s) |
eng |
Direitos |
info:eu-repo/semantics/restrictedAccess |
Fonte |
O'Neill , S , Woods , R , Marshall , A & Zhang , Q 2011 , ' A Scalable and Programmable Modular Traffic Manager Architecture ' ACM Transactions on Reconfigurable Technology and Systems , vol 4 , no. 2 , 14 . DOI: 10.1145/1968502.1968505 |
Palavras-Chave | #/dk/atira/pure/subjectarea/asjc/1700 #Computer Science(all) |
Tipo |
article |