Shortening design time through multiplatform simulations with a portable OpenCL golden-model: the LDPC decoder case

Hardware designers and engineers typically need to explore a multi-parametric design space in order to find the best configuration for their designs using simulations that can take weeks to months to complete. For example, designers of special purpose chips need to explore parameters such as the optimal bitwidth and data representation. This is the case for the development of complex algorithms such as Low-Density Parity-Check (LDPC) decoders used in modern communication systems. Currently, high-performance computing offers a wide set of acceleration options, that range from multicore CPUs to graphics processing units (GPUs) and FPGAs. Depending on the simulation requirements, the ideal architecture to use can vary. In this paper we propose a new design flow based on OpenCL, a unified multiplatform programming model, which accelerates LDPC decoding simulations, thereby significantly reducing architectural exploration and design time. OpenCL-based parallel kernels are used without modifications or code tuning on multicore CPUs, GPUs and FPGAs. We use SOpenCL (Silicon to OpenCL), a tool that automatically converts OpenCL kernels to RTL for mapping the simulations into FPGAs. To the best of our knowledge, this is the first time that a single, unmodified OpenCL code is used to target those three different platforms. We show that, depending on the design parameters to be explored in the simulation, on the dimension and phase of the design, the GPU or the FPGA may suit different purposes more conveniently, providing different acceleration factors. For example, although simulations can typically execute more than 3x faster on FPGAs than on GPUs, the overhead of circuit synthesis often outweighs the benefits of FPGA-accelerated execution.

Logic and Memory Design Based on Unequal Error Protection for Voltage-scalable, Robust and Adaptive DSP Systems

In this paper, we propose a system level design approach considering voltage over-scaling (VOS) that achieves error resiliency using unequal error protection of different computation elements, while incurring minor quality degradation. Depending on user specifications and severity of process variations/channel noise, the degree of VOS in each block of the system is adaptively tuned to ensure minimum system power while providing "just-the-right" amount of quality and robustness. This is achieved, by taking into consideration block level interactions and ensuring that under any change of operating conditions, only the "less-crucial" computations, that contribute less to block/system output quality, are affected. The proposed approach applies unequal error protection to various blocks of a system-logic and memory-and spans multiple layers of design hierarchy-algorithm, architecture and circuit. The design methodology when applied to a multimedia subsystem shows large power benefits ( up to 69% improvement in power consumption) at reasonable image quality while tolerating errors introduced due to VOS, process variations, and channel noise.

Rapid design of discrete orthonormal wavelet transforms using silicon IP components

A rapid design methodology for orthonormal wavelet transform cores has been developed. This methodology is based on a generic, scaleable architecture utilising time-interleaved coefficients for the wavelet transform filters. The architecture has been captured in VHDL and parameterised in terms of wavelet family, wavelet type, data word length and coefficient word length. The control circuit is embedded within the cores and allows them to be cascaded without any interface glue logic for any desired level of decomposition. Case studies for stand alone and cascaded silicon cores for single and multi-stage wavelet analysis respectively are reported. The design time to produce silicon layout of a wavelet based system has been reduced to typically less than a day. The cores are comparable in area and performance to handcrafted designs. The designs are portable across a range of foundries and are also applicable to FPGA and PLD implementations.

Transcending Boundaries of Creativity: Active learning in the Design Studio

This essay investigates the changing dynamics of interaction and paradigm of communication in the design studio. It analyses the process of practical implementation of interactive tools in architectural education which placed the
diversity of students’ cultural experiences, contextual awareness and individual interests as crucial resource for design innovation and inquiry. Building on Brian Lawson’s thesis on creativity in design thinking, this research project undertook
comprehensive investigation of students’ satisfaction of their roles in the studio and the room for liberal thought they are given to elaborate on genuine approach to architectural matters. The cyclical development of interactive learning strategy is explored through two different settings: first, it analyses architectural students’ position as passive/active in the studio, considering their relationships with tutors’ ideals; second, it reports on empirical strategy of students-led workshops at British schools of architecture, during which students have taken the lead of their creative design agenda. The practical implementation of interactive learning tools proved influential in helping students to personalize their design direction and to build a sense of confidence and independence.

Enhancing design space exploration by extending CPU/GPU specifications onto FPGAs

The design cycle for complex special-purpose computing systems is extremely costly and time-consuming. It involves a multiparametric design space exploration for optimization, followed by design verification. Designers of special purpose VLSI implementations often need to explore parameters, such as optimal bitwidth and data representation, through time-consuming Monte Carlo simulations. A prominent example of this simulation-based exploration process is the design of decoders for error correcting systems, such as the Low-Density Parity-Check (LDPC) codes adopted by modern communication standards, which involves thousands of Monte Carlo runs for each design point. Currently, high-performance computing offers a wide set of acceleration options that range from multicore CPUs to Graphics Processing Units (GPUs) and Field Programmable Gate Arrays (FPGAs). The exploitation of diverse target architectures is typically associated with developing multiple code versions, often using distinct programming paradigms. In this context, we evaluate the concept of retargeting a single OpenCL program to multiple platforms, thereby significantly reducing design time. A single OpenCL-based parallel kernel is used without modifications or code tuning on multicore CPUs, GPUs, and FPGAs. We use SOpenCL (Silicon to OpenCL), a tool that automatically converts OpenCL kernels to RTL in order to introduce FPGAs as a potential platform to efficiently execute simulations coded in OpenCL. We use LDPC decoding simulations as a case study. Experimental results were obtained by testing a variety of regular and irregular LDPC codes that range from short/medium (e.g., 8,000 bit) to long length (e.g., 64,800 bit) DVB-S2 codes. We observe that, depending on the design parameters to be simulated, on the dimension and phase of the design, the GPU or FPGA may suit different purposes more conveniently, thus providing different acceleration factors over conventional multicore CPUs.

Architecture as Pedagogy: Alive and Kicking

This workshop draws on an emerging collaborative body of research by Lovett, Morrow and McClean that aims to understand architecture and its processes as a form of pedagogical practice: a civic pedagogy.

Architectural education can be valued not only as a process that delivers architecture-specific skills and knowledges, but also as a process that transforms people into critically active contributors to society. We are keen to examine how and where those skills are developed in architectural education and trace their existence and/or application within practice. We intend to examine whether some architectural and spatial practices are intrinsically pedagogical in their nature and how the level of involvement of clients, users and communities can mimic the project-based learning of architectural education – in particularly in the context of ‘live project learning’

1. This workshop begins with a brief discussion paper from Morrow that sets out the arguments behind why and how architecture can be understood as pedagogy. It will do so by presenting firstly the relationship between architectural practice and pedagogy, drawing out both contemporary and historical examples of architecture and architects acting pedagogically. It will also consider some other forms of creative practice that explicitly frame themselves pedagogically, and focus on participatory approaches in architectural practice that overlap with inclusive and live pedagogies, concluding with a draft and tentative abstracted pedagogical framework for architectural practice.

2. Lovett will examine practices of architectural operation that have a pedagogical approach, or which recognise within themselves an educational subtext/current. He is most interested in a 'liveness' beyond the 'Architectural Education' of university institutions. The presentation will question the scope for both spatial empowerment / agency and a greater understanding and awareness of the value of good design when operating as architects with participant-clients younger than 18, older than 25 or across varied parts of society. Positing that the learning might be greatest when there are no prescribed 'Learning Outcomes' and that such work might depend on risk-taking and playfulness, the presentation will be a curated showcase drawing on his own ongoing work.

Both brief presentations will inform the basis of the workshop’s discussion which hopes to draw on participants views and expereinces to enrich the research process. The intention is that the overall workshop will lead to a call for contributors and respondents to a forthcoming publication on ‘Architecture as Pedagogy’.

Investigation of thermal resistance and bridging in examples of contemporary and vernacular solid wall architecture

Contemporary architecture has tended to increase envelope insulation levels in an unceasing effort to reduce U-values. Traditional masonry architecture in contrast was devoid of insulation, except for the inherent insulative nature of vernacular materials. Also the consistency of the outer membrane of the building skin diminished any impact due to bridging. In contemporary highly insulated walls bridges are numerous due to the necessity to bind inner and outer structural skins through insulation layers. This paper examines thermal bridging in an example of contemporary façade design and compares it with an example of traditional vernacular architecture currently being researched which is characterized by a lack of bridging elements. Focus is given to heavy weight materials of high thermal mass, which appropriately for passive architecture help moderate fluctuations in internal temperature. In an extensive experimental study samples of highly insulated precast concrete sandwich panels and lime rendered masonry walls are tested in a guarded hot-box. The building construction methods are compared for static and dynamic thermal transmittance, via heat flux and surface temperature differential measurements. Focus is given to the differential heat loss due to the thermal bridging in the sandwich panels and its associated impact on overall heat loss relative to traditional masonry construction.

Lost in Transition? Emerging forms of residential architecture in Kathmandu

Kathmandu has been the last few cities in the world which retained its medieval urban culture up until twentieth century. Various Hindu and Buddhist religious practices shaped the arrangement of houses, roads and urban spaces giving the city a distinctive physical form, character and a unique oriental nativeness. In recent decades, the urban culture of the city has been changing with the forces of urbanisation and globalisation and the demand for new buildings and spaces. New residential design is increasingly dominated by distinctive patterns of Western suburban ideal comprising detached or semi-detached homes and high rise tower blocks. This architectural iconoclasm can be construed as a rather crude response to the indigenous spaces and builtform. The paper attempts to dismantle the current tension between traditional and contemporary 'culture' (and hence society) and housing (or builtform) in Kathmandu by engaging in a discussion that cuts across space, time and meaning of building. The paper concludes that residential architecture in Kathmandu today stands disoriented and lost in the transition.

A Scheme Design of Cloud + End Technology in Demand Side Management

Demand Side Management (DSM) plays an important role in Smart Grid. It has large scale access points, massive users, heterogeneous infrastructure and dispersive participants. Moreover, cloud computing which is a service model is characterized by resource on-demand, high reliability and large scale integration and so on and the game theory is a useful tool to the dynamic economic phenomena. In this study, a scheme design of cloud + end technology is proposed to solve technical and economic problems of the DSM. The architecture of cloud + end is designed to solve technical problems in the DSM. In particular, a construct model of cloud + end is presented to solve economic problems in the DSM based on game theories. The proposed method is tested on a DSM cloud + end public service system construction in a city of southern China. The results demonstrate the feasibility of these integrated solutions which can provide a reference for the popularization and application of the DSM in china.

On the statistical memory architecture exploration and optimization

The worsening of process variations and the consequent increased spreads in circuit performance and consumed power hinder the satisfaction of the targeted budgets and lead to yield loss. Corner based design and adoption of design guardbands might limit the yield loss. However, in many cases such methods may not be able to capture the real effects which might be way better than the predicted ones leading to increasingly pessimistic designs. The situation is even more severe in memories which consist of substantially different individual building blocks, further complicating the accurate analysis of the impact of variations at the architecture level leaving many potential issues uncovered and opportunities unexploited. In this paper, we develop a framework for capturing non-trivial statistical interactions among all the components of a memory/cache. The developed tool is able to find the optimum memory/cache configuration under various constraints allowing the designers to make the right choices early in the design cycle and consequently improve performance, energy, and especially yield. Our, results indicate that the consideration of the architectural interactions between the memory components allow to relax the pessimistic access times that are predicted by existing techniques.

FPGA based Streaming Image Processing Processor (SIPPro) architecture to accelerate data intensive applications

Current data-intensive image processing applications push traditional embedded architectures to their limits. FPGA based hardware acceleration is a potential solution but the programmability gap and time consuming HDL design flow is significant. The proposed research approach to develop “FPGA based programmable hardware acceleration platform” that uses, large number of Streaming Image processing Processors (SIPPro) potentially addresses these issues. SIPPro is pipelined in-order soft-core processor architecture with specific optimisations for image processing applications. Each SIPPro core uses 1 DSP48, 2 Block RAMs and 370 slice-registers, making the processor as compact as possible whilst maintaining flexibility and programmability. It is area efficient, scalable and high performance softcore architecture capable of delivering 530 MIPS per core using Xilinx Zynq SoC (ZC7Z020-3). To evaluate the feasibility of the proposed architecture, a Traffic Sign Recognition (TSR) algorithm has been prototyped on a Zedboard with the color and morphology operations accelerated using multiple SIPPros. Simulation and experimental results demonstrate that the processing platform is able to achieve a speedup of 15 and 33 times for color filtering and morphology operations respectively, with a significant reduced design effort and time.

Design of a Virtual Reality Framework for Maintainability and assemblability test of complex systems

This paper presents a unique environment whose features are able to satisfy requirements for both virtual maintenance and virtual manufacturing through the conception of original virtual reality (VR) architecture. Virtual Reality for the Maintainability and Assemblability Tests (VR_MATE) encompasses VR hardware and software and a simulation manager which allows customisation of the architecture itself as well as interfacing with a wide range of devices employed in the simulations. Two case studies are presented to illustrate VR_MATE's unique ability to allow for both maintainability tests and assembly analysis of an aircraft carriage and a railway coach cooling system respectively. The key impact of this research is the demonstration of the potentialities of using VR techniques in industry and its multiple applications despite the subjective character within the simulation. VR_MATE has been presented as a framework to support the strategic and operative objectives of companies to reduce product development time and costs whilst maintaining product quality for applications which would be too expensive to simulate and evaluate in the real world.