A self-structured adaptive decision feedback equalizer

In a decision feedback equalizer (DFE), the structural parameters, including the decision delay, the feedforward filter (FFF), and feedback filter (FBF) lengths, must be carefully chosen, as they greatly influence the performance. Although the FBF length can be set as the channel memory, there is no closed-form expression for the FFF length and decision delay. In this letter, first we analytically show that the two-dimensional search for the optimum FFF length and decision delay can be simplified to a one-dimensional search and then describe a new adaptive DFE where the optimum structural parameters can he self-adapted.

Adaptive data echo cancellation using cost function adaptation

For a digital echo canceller it is desirable to reduce the adaptation time, during which the transmission of useful data is not possible. LMS is a non-optimal algorithm in this case as the signals involved are statistically non-Gaussian. Walach and Widrow (IEEE Trans. Inform. Theory 30 (2) (March 1984) 275-283) investigated the use of a power of 4, while other research established algorithms with arbitrary integer (Pei and Tseng, IEEE J. Selected Areas Commun. 12(9)(December 1994) 1540-1547) or non-quadratic power (Shah and Cowan, IEE.Proc.-Vis. Image Signal Process. 142 (3) (June 1995) 187-191). This paper suggests that continuous and automatic, adaptation of the error exponent gives a more satisfactory result. The family of cost function adaptation (CFA) stochastic gradient algorithm proposed allows an increase in convergence rate and, an improvement of residual error. As special case the staircase CFA algorithm is first presented, then the smooth CFA is developed. Details of implementations are also discussed. Results of simulation are provided to show the properties of the proposed family of algorithms. (C) 2000 Elsevier Science B.V. All rights reserved.

MSGR-based Low Latency Complex Matrix Inversion Architecture

This paper presents a matrix inversion architecture based on the novel Modified Squared Givens Rotations (MSGR) algorithm, which extends the original SGR method to complex valued data, and also corrects erroneous results in the original SGR method when zeros occur on the diagonal of the matrix either initially or during processing. The MSGR algorithm also avoids complex dividers in the matrix inversion, thus minimising the complexity of potential real-time implementations. A systolic array architecture is implemented and FPGA synthesis results indicate a high-throughput low-latency complex matrix inversion solution. © 2008 IEEE.

Hierarchical synthesis of complex DSP functions on FPGAs

SoC systems are now being increasingly constructed using a hierarchy of subsystems or silicon Intellectual Property (IP) cores. The key challenge is to use these cores in a highly efficient manner which can be difficult as the internal core structure may not be known. A design methodology based on synthesizing hierarchical circuit descriptions is presented. The paper employs the MARS synthesis scheduling algorithm within the existing IRIS synthesis flow and details how it can be enhanced to allow for design exploration of IP cores. It is shown that by accessing parameterised expressions for the datapath latencies in the cores, highly efficient FPGA solutions can be achieved. Hardware sharing at both the hierarchical and flattened levels is explored for a normalized lattice filter and results are presented.

Online CORDIC algorithm and VLSI architecture for implementing QR-array processors

A novel most significant digit first CORDIC architecture is presented that is suitable for the VLSI design of systolic array processor cells for performing QR decomposition. This is based on an on-line CORDIC algorithm with a constant scale factor and a latency independent of the wordlength. This has been derived through the extension of previously published CORDIC algorithms. It is shown that simplifying the calculation of convergence bounds also greatly simplifies the derivation of suitable VLSI architectures. Design studies, based on a 0.35-µ CMOS standard cell process, indicate that 20 such QR processor cells operating at rates suitable for radar beamfoming can be readily accommodated on a single chip.

Linear QR architecture for a single chip adaptive beamformer

This paper presents the design of a novel single chip adaptive beamformer capable of performing 50 Gflops, (Giga-floating-point operations/second). The core processor is a QR array implemented on a fully efficient linear systolic architecture, derived using a mapping that allows individual processors for boundary and internal cell operations. In addition, the paper highlights a number of rapid design techniques that have been used to realise this system. These include an architecture synthesis tool for quickly developing the circuit architecture and the utilisation of a library of parameterisable silicon intellectual property (IP) cores, to rapidly develop detailed silicon designs.

A Cyclotomic Lattice Based Quasi-Orthogonal STBC for Eight Transmit Antennas

In this letter, we propose a lattice-based full diversity design for rate-one quasi-orthogonal space time block codes (QSTBC) to obtain an improved diversity product for eight transmit antennas where the information bits are mapped into 4-D lattice points instead of the common modulation constellations. Particularly, the diversity product of the proposed code is directly determined by the minimum Euclidean distance of the used lattice and can be improved by using the lattice packing. We show analytically and by using simulation results that the proposed code achieves a larger diversity product than the rate-one QSTBCs reported previously.

A New Restricted Full-Rank Single-Symbol Decodable Design for Four Transmit Antennas

Recently, a single-symbol decodable transmit strategy based on preprocessing at the transmitter has been introduced to decouple the quasi-orthogonal space-time block codes (QOSTBC) with reduced complexity at the receiver [9]. Unfortunately, it does not achieve full diversity, thus suffering from significant performance loss. To tackle this problem, we propose a full diversity scheme with four transmit antennas in this letter. The proposed code is based on a class of restricted full-rank single-symbol decodable design (RFSDD) and has many similar characteristics as the coordinate interleaved orthogonal designs (CIODs), but with a lower peak-to-average ratio (PAR).

On the Uncoded BER Performance Bound of the IEEE 802.16d Channel

In this letter, the performance bound of the IEEE 802.16d channel is examined analytically in order to gain an insight into its theoretical potential. Different design strategies, such as orthogonal frequency division multiplexing (OFDM) and single-carrier frequency-domain equalization (SC-FDE), time-domain decision feedback equalization (DFE), and sphere decoder (SD) techniques are discussed and compared to the theoretical bound.

Application of Jacobi algorithm for ISI channels

Here, the Jacobi iterative algorithm is applied to combat intersymbol interference (ISI) caused by frequency-selective channels. The performance bound of the equaliser is analysed in order to gain an insight into its asymptotic behaviour. Because of the error propagation problem, the potential of this algorithm is not reached in an uncoded system. However, its extension to a coded system with the application of the turbo-processing principle results in a new turbo equalisation algorithm, which demonstrates comparable performance with reduced complexity compared with some existing filter-based turbo equalisation schemes; and superior performance compared with some frequency domain solutions, such as orthogonal frequency division multiplexing and single-carrier frequency domain equalisation.

The exponentiated convex variable step-size (ECVSS) algorithm

For some time there is a large interest in variable step-size methods for adaptive filtering. Recently, a few stochastic gradient algorithms have been proposed, which are based on cost functions that have exponential dependence on the chosen error. However, we have experienced that the cost function based on exponential of the squared error does not always satisfactorily converge. In this paper we modify this cost function in order to improve the convergence of exponentiated cost function and the novel ECVSS (exponentiated convex variable step-size) stochastic gradient algorithm is obtained. The proposed technique has attractive properties in both stationary and abrupt-change situations. (C) 2010 Elsevier B.V. All rights reserved.

On-line Emotion Recognition in a 3-D Activation-Valence-Time Continuum using Acoustic and Linguistic Cues

For many applications of emotion recognition, such as virtual agents, the system must select responses while the user is speaking. This requires reliable on-line recognition of the user’s affect. However most emotion recognition systems are based on turnwise processing. We present a novel approach to on-line emotion recognition from speech using Long Short-Term Memory Recurrent Neural Networks. Emotion is recognised frame-wise in a two-dimensional valence-activation continuum. In contrast to current state-of-the-art approaches, recognition is performed on low-level signal frames, similar to those used for speech recognition. No statistical functionals are applied to low-level feature contours. Framing at a higher level is therefore unnecessary and regression outputs can be produced in real-time for every low-level input frame. We also investigate the benefits of including linguistic features on the signal frame level obtained by a keyword spotter.