Generic low-latency NoC router architecture for FPGA computing systems

A novel cost-effective and low-latency wormhole router for packet-switched NoC designs, tailored for FPGA, is presented. This has been designed to be scalable at system level to fully exploit the characteristics and constraints of FPGA based systems, rather than custom ASIC technology. A key feature is that it achieves a low packet propagation latency of only two cycles per hop including both router pipeline delay and link traversal delay - a significant enhancement over existing FPGA designs - whilst being very competitive in terms of performance and hardware complexity. It can also be configured in various network topologies including 1-D, 2-D, and 3-D. Detailed design-space exploration has been carried for a range of scaling parameters, with the results of various design trade-offs being presented and discussed. By taking advantage of abundant buildin reconfigurable logic and routing resources, we have been able to create a new scalable on-chip FPGA based router that exhibits high dimensionality and connectivity. The architecture proposed can be easily migrated across many FPGA families to provide flexible, robust and cost-effective NoC solutions suitable for the implementation of high-performance FPGA computing systems. © 2011 IEEE.

Shifting Ground:Beyond National Architecture

The Irish Pavilion at the Venice Architecture Biennale 2012 charts a position for Irish architecture in a global culture where the modes of production of architecture are radically altered. Ireland is one of the most globalised countries in the world, yet it has developed a national culture of architecture derived from local place as a material construct. We now have to evolve our understanding in the light of the globalised nature of economic processes and architectural production which is largely dependent on internationally networked flows of products, data, and knowledge. We have just begun to represent this situation to ourselves and others. How should a global architecture be grounded culturally and philosophically? How does it position itself outside of shared national reference points?
heneghan peng architects were selected as participants because they are working across three continents on a range of competition-winning projects. Several of these are in sensitive and/or symbolic sites that include three UNESCO World Heritage sites, including the Grand Egyptian Museum in Cairo, the Giants Causeway Visitor Centre in Northern Ireland, and the new Rhine Bridge near Lorelei.
Our dialogue led us to discussing the universal languages of projective geometry and number are been shared by architects and related professionals. In the work of heneghan peng, the specific embodiment of these geometries is carefully calibrated by the choice of materials and the detailed design of their physical performance on site. The stone facade of the Giant’s Causeway Visitor Centre takes precise measure of the properties of the volcanic basalt seams from which it is hewn. The extraction of the stone is the subject of the pavilion wall drawings which record the cutting of stones to create the façade of the causeway centre.
We also identified water as an element which is shared across the different sites. Venice is a perfect place to take measure of this element which suggests links to another site – the Nile Valley which was enriched by the annual flooding of the River Nile. An ancient Egyptian rod for measuring the water level of the Nile inspired the design of the Nilometre - a responsive oscillating bench that invites visitors to balance their respective weights. This action embodies the ways of thinking that are evolving to operate in the globalised world, where the autonomous architectural object is dissolving into an expanded field of conceptual rules and systems. The bench constitutes a shifting ground located in the unstable field of Venice. It is about measurement and calibration of the weight of the body in relation to other bodies; in relation to the site of the installation; and in relation to water. The exhibit is located in the Artiglierie section of the Arsenale. Its level is calibrated against the mark of the acqua alta in the adjacent brickwork of the building which embodies a liminal moment in the fluctuating level of the lagoon.
The weights of bodies, the level of water, changes over time, are constant aspects of design across cultures and collectively they constitute a common ground for architecture - a ground shared with other design professionals. The movement of the bench required complex engineering design and active collaboration between the architects, engineers and fabricators. It is a kind of prototype – a physical object produced from digital data that explores the mathematics at play – the see-saw motion invites the observer to become a participant, to give it a test drive. It shows how a simple principle can generate complex effects that are difficult to predict and invites visitors to experiment and play with them.

Design and Implementation of a Measurement-Based Policy-Driven Resource Management Framework For Converged Networks

This paper presents the design and implementation of a measurement-based QoS and resource management framework, CNQF (Converged Networks’ QoS Management Framework). CNQF is designed to provide unified, scalable QoS control and resource management through the use of a policy-based network
management paradigm. It achieves this via distributed functional entities that are deployed to co-ordinate the resources of the transport network through centralized policy-driven decisions supported by measurement-based control architecture. We present the CNQF architecture, implementation of the
prototype and validation of various inbuilt QoS control mechanisms using real traffic flows on a Linux-based experimental test bed.

Portrush: Architecture for the North Irish Coast

The North Irish coast resembles one of the unique landscapes that define the scenic character of the place. To understand place you need to engage with stories and histories behind it. The search for Portrush has to start from Ulster. This book offers a journey to explore histories, traditions, festivities and the architecture of the Irish town. Approaching Portrush as a field of experimental architectural studio, the studio at Queen’s University Belfast teamed up to rediscover the Irish coastal condition and have a rethink about the origins and ingredients of Irish architecture and landscape. This book records and discusses this ambitious project and its outcome. Divided into two parts, the book introduces a comprehensive contextual and historical investigation into the heritage, culture and architecture followed by a display of students’ theoretical encounters and designs.

Multi-standard sub-pixel interpolation architecture for video motion estimation

A new domain-specific reconfigurable sub-pixel interpolation architecture for multi-standard video Motion Estimation (ME) is presented. The mixed use of parallel and serial-input FIR filters achieves high throughput rate and efficient silicon utilisation. Flexibility has been achieved by using a multiplexed reconfigurable data-path controlled by a selection signal. Silicon design studies show that this can be implemented using 34.8K gates with area and performance that compares very favourably with existing fixed solutions based solely on the H.264 standard. ©2008 IEEE.

Waste Management and Sustainability during the Design Phase of a Construction Project: A Qualitative Review

Waste management and sustainability are two core underlying philosophies that the construction sector must acknowledge and implement; however, this can prove difficult and time consuming. To this end, the aim of this paper is to examine waste management strategies and the possible benefits, advantages and disadvantages to their introduction and use, while also to examine any inter-relationship with sustainability, particularly at the design stage. The purpose of this paper is to gather, examine and review published works and investigate factors which influence economic decisions at the design phase of a construction project. In addressing this aim, a three tiered sequential research approach is adopted; in-depth literature review, interviews/focus groups and qualitative analysis. The resulting data is analyzed, discussed, with potential conclusions identified; paying particular attention to implications for practice within architectural firms. This research is of importance, particularly to the architectural sector, as it can add to the industry’s understanding of the design process, while also considering the application and integration of waste management into the design procedure. Results indicate that the researched topic had many advantages but also had inherent disadvantages. It was found that the potential advantages outweighed disadvantages, but uptake within industry was still slow and that better promotion and their benefits to; sustainability, the environment, society and the industry were required.

Two-Way Relaying Networks with Wireless Power Transfer: Policies Design and Throughput Analysis

This paper exploits an amplify-and-forward (AF) two-way relaying network (TWRN), where an energy constrained relay node harvests energy with wireless power transfer. Two bidirectional protocols, multiple access broadcast (MABC) protocol and time division broadcast (TDBC) protocol, are considered. Three wireless power transfer policies, namely, 1) dual-source (DS) power transfer; 2) single-fixed-source (SFS) power transfer; and 3) single-best-source (SBS) power transfer are proposed and well-designed based on time switching receiver architecture. We derive analytical expressions to determine the throughput both for delay-limited transmission and delay-tolerant transmission. Numerical results corroborate our analysis and show that MABC protocol achieves a higher throughput than TDBC protocol. An important observation is that SBS policy offers a good tradeoff between throughput and power.

Architecture from the dogs …

In this chapter Morrow talks of her return to Northern Ireland to 2003 and how her involvement in establishing a new school of architecture and a recent suite of interdisciplinary masters has led her to consider the relationship between the post-conflict context, architectural practice and its education. She examines the consequences of not facing the effects of conflict; the impact on societal and architectural creativity; and the potential for live project pedagogy to evolve effective models of socio-spatial rehearsals. She concludes with some strategies for schools of architecture that wish to feed and be fed by their context. This is a personalized commentary that teeters somewhere between deep-seated frustration with a blind-folded profession and sustained belief in architectural education’s potential to offer more than built solutions.

Low-power DWT-based quasi-averaging algorithm and architecture for epileptic seizure detection

In this paper, we have developed a low-complexity algorithm for epileptic seizure detection with a high degree of accuracy. The algorithm has been designed to be feasibly implementable as battery-powered low-power implantable epileptic seizure detection system or epilepsy prosthesis. This is achieved by utilizing design optimization techniques at different levels of abstraction. Particularly, user-specific critical parameters are identified at the algorithmic level and are explicitly used along with multiplier-less implementations at the architecture level. The system has been tested on neural data obtained from in-vivo animal recordings and has been implemented in 90nm bulk-Si technology. The results show up to 90 % savings in power as compared to prevalent wavelet based seizure detection technique while achieving 97% average detection rate. Copyright 2010 ACM.

Design methodology for low power and arametric robustness through output-quality modulation:Application to color-interpolation filtering

Power dissipation and robustness to process variation have conflicting design requirements. Scaling of voltage is associated with larger variations, while Vdd upscaling or transistor upsizing for parametric-delay variation tolerance can be detrimental for power dissipation. However, for a class of signal-processing systems, effective tradeoff can be achieved between Vdd scaling, variation tolerance, and output quality. In this paper, we develop a novel low-power variation-tolerant algorithm/architecture for color interpolation that allows a graceful degradation in the peak-signal-to-noise ratio (PSNR) under aggressive voltage scaling as well as extreme process variations. This feature is achieved by exploiting the fact that all computations used in interpolating the pixel values do not equally contribute to PSNR improvement. In the presence of Vdd scaling and process variations, the architecture ensures that only the less important computations are affected by delay failures. We also propose a different sliding-window size than the conventional one to improve interpolation performance by a factor of two with negligible overhead. Simulation results show that, even at a scaled voltage of 77% of nominal value, our design provides reasonable image PSNR with 40% power savings. © 2006 IEEE.

HERQULES:System level cross-layer design exploration for efficient energy-quality trade-offs

In this paper, we present a unique cross-layer design framework that allows systematic exploration of the energy-delay-quality trade-offs at the algorithm, architecture and circuit level of design abstraction for each block of a system. In addition, taking into consideration the interactions between different sub-blocks of a system, it identifies the design solutions that can ensure the least energy at the "right amount of quality" for each sub-block/system under user quality/delay constraints. This is achieved by deriving sensitivity based design criteria, the balancing of which form the quantitative relations that can be used early in the system design process to evaluate the energy efficiency of various design options. The proposed framework when applied to the exploration of energy-quality design space of the main blocks of a digital camera and a wireless receiver, achieves 58% and 33% energy savings under 41% and 20% error increase, respectively. © 2010 ACM.

VEDA:Variation-aware energy-efficient discrete Wavelet Transform architecture

In this paper, we present a unified approach to an energy-efficient variation-tolerant design of Discrete Wavelet Transform (DWT) in the context of image processing applications. It is to be noted that it is not necessary to produce exactly correct numerical outputs in most image processing applications. We exploit this important feature and propose a design methodology for DWT which shows energy quality tradeoffs at each level of design hierarchy starting from the algorithm level down to the architecture and circuit levels by taking advantage of the limited perceptual ability of the Human Visual System. A unique feature of this design methodology is that it guarantees robustness under process variability and facilitates aggressive voltage over-scaling. Simulation results show significant energy savings (74% - 83%) with minor degradations in output image quality and avert catastrophic failures under process variations compared to a conventional design. © 2010 IEEE.

An optimal algorithm for low power multiplierless FIR filter design using chebychev criterion

In this paper, we propose a novel finite impulse response (FIR) filter design methodology that reduces the number of operations with a motivation to reduce power consumption and enhance performance. The novelty of our approach lies in the generation of filter coefficients such that they conform to a given low-power architecture, while meeting the given filter specifications. The proposed algorithm is formulated as a mixed integer linear programming problem that minimizes chebychev error and synthesizes coefficients which consist of pre-specified alphabets. The new modified coefficients can be used for low-power VLSI implementation of vector scaling operations such as FIR filtering using computation sharing multiplier (CSHM). Simulations in 0.25um technology show that CSHM FIR filter architecture can result in 55% power and 34% speed improvement compared to carry save multiplier (CSAM) based filters.

Design methodology to trade off power, output quality and error resiliency: Application to color interpolation filtering

Power dissipation and tolerance to process variations pose conflicting design requirements. Scaling of voltage is associated with larger variations, while Vdd upscaling or transistor up-sizing for process tolerance can be detrimental for power dissipation. However, for certain signal processing systems such as those used in color image processing, we noted that effective trade-offs can be achieved between Vdd scaling, process tolerance and "output quality". In this paper we demonstrate how these tradeoffs can be effectively utilized in the development of novel low-power variation tolerant architectures for color interpolation. The proposed architecture supports a graceful degradation in the PSNR (Peak Signal to Noise Ratio) under aggressive voltage scaling as well as extreme process variations in. sub-70nm technologies. This is achieved by exploiting the fact that some computations are more important and contribute more to the PSNR improvement compared to the others. The computations are mapped to the hardware in such a way that only the less important computations are affected by Vdd-scaling and process variations. Simulation results show that even at a scaled voltage of 60% of nominal Vdd value, our design provides reasonable image PSNR with 69% power savings.