Asymmetric information without common priors: an indirect evolutionary analysis of quantity competition

The common prior assumption justifies private beliefs as posterior probabilities when updating a common prior based on individual information. We dispose of the common prior assumption for a homogeneous oligopoly market with uncertain costs and firms entertaining arbitrary priors about other firms' cost-type. We show that true prior beliefs can not be evolutionarily stable when truly expected profit measures (reproductive) success.

Parimutuel betting under asymmetric information

This paper examines simple parimutuel betting games under asymmetric information, with particular attention to differences between markets in which bets are submitted simultaneously versus sequentially. In the simultaneous parimutuel betting market, all (symmetric and asymmetric) Bayesian-Nash equilibria are generically characterized as a function of the number of bettors and the quality of their private information. There always exists a separating equilibrium, in which all bettors follow their private signals. This equilibrium is unique if the number of bettors is sufficiently large. In the sequential framework, earlier bets have information externalities, because they may reveal private information of bettors. They also have payoff externalities, because they affect the betting odds. One effect of these externalities is that the separating equilibrium disappears if the number of betting periods is sufficiently large. (C) 2006 Elsevier B.V. All rights reserved.

High performance VLSI architecture for division and square root

A novel high performance bit parallel architecture to perform square root and division is proposed. Relevant VLSI design issues have been addressed. By employing redundant arithmetic and a semisystolic schedule, the throughput has been made independent of the size of the array.

A VLSI architecture for multiplication, division and square root

A high-performance VLSI architecture to perform combined multiply-accumulate, divide, and square root operations is proposed. The circuit is highly regular, requires only minimal control, and can be reconfigured for every cycle. The execution time for each operation is the same. The combination of redundancy and pipelining results in a throughput independent of the wordsize of the array. With current CMOS technology, throughput rates in excess of 80 million operations per second are achievable.

Fast VLSI algorithms for division and square root

Real time digital signal processing demands high performance implementations of division and square root. This can only be achieved by the design of fast and efficient arithmetic algorithms which address practical VLSI architectural design issues. In this paper, new algorithms for division and square root are described. The new schemes are based on pre-scaling the operands and modifying the classical SRT method such that the result digits and the remainders are computed concurrently and the computations in adjacent rows are overlapped. Consequently, their performance exceeds that of the SRT methods. The hardware cost for higher radices is considerably more than that of the SRT methods but for many applications, this is not prohibitive. A system of equations is presented which enables both an analysis of the method for any radix and the parameters of implementations to be easily determined. This is illustrated for the case of radix 2 and radix 4. In addition, a highly regular array architecture combining the division and square root method is described. © 1994 Kluwer Academic Publishers.

New algorithms and VLSI architectures for SRT division and square root

In real time digital signal processing, high performance modules for division and square root are essential if many powerful algorithms are to be implemented. In this paper, a new radix 2 algorithms for SRT division and square root are developed. For these new schemes, the result digits and the residuals are computed concurrently and the computations in adjacent rows are overlapped. Consequently, their performance should exceed that of the radix 2 SRT methods. VLSI array architectures to implement the new division and square root schemes are also presented.

Chiral supported ionic liquid phase (CSILP) catalysts for greener asymmetric hydrogenation processes

Chiral supported ionic liquid phase (CSILP) catalysts were prepared by physical adsorption (within highly porous carbons or mesoporous silica) of Ir, Ru and Rh complexes as IrCl(COD)-(S, S)-BDPP, [IrCl-(S)-BINAP](2), RuCl(p-cymene)[(S, S)-Ts-DPEN], RuOTf(p-cymene)[(S, S)-Ts-DPEN], [Rh(COD)(S, S)-DIPAMP][BF4], and [Rh(COD)(R, R)-Me-DuPHOS][BF4]. For the syntheses of CSILP catalysts [EMIM][NTf2], [BMIM][BF4] and [BMIM][PF6] ionic liquids were used. Comparative homogeneous and heterogeneous experiments were carried out using the asymmetric hydrogenation of double -C N- and -C C- bonds in trimethylindolenine, 2-methylquinoline and dimethylitaconate, respectively. The conversion and enantioselectivity was found to depend on the nature of the complex (metal and ligand), the immobilization method used, nature of the ionic liquid, nature of the support and the experimental conditions. (C) 2012 Elsevier B.V. All rights reserved.