92 resultados para modular flap
Resumo:
Purpose: A number of cytotoxic chemotherapy agents tested at low concentrations show antiangiogenic properties with limited cytotoxicity, e.g., cyclophosphamide, tirapazamine, and mitoxantrone. AQ4N is a bioreductive alkylaminoanthraquinone that is cytotoxic when reduced to AQ4; hence, it can be used to target hypoxic tumor cells. AQ4N is structurally similar to mitoxantrone and was evaluated for antiangiogenic properties without the need for bioreduction.
Experimental Design:The effect of AQ4N and fumagillin on human microvascular endothelial cells (HMEC-1) was measured using a variety ofin vitro assays, i.e., 3-(4,5-dimethylthiazol-2-yl)- 2,5-diphenyltetrazolium bromide, wound scrape, tubule formation, rat aortic ring, and invasion assays. Low-dose AQ4N (20 mg/kg) was also given in vivo to mice bearing a tumor in a dorsal skin flap.
Results:AQ4N (10-11to10-5mol/L) hadno effect on HMEC-1viability. AQ4N (10-9to10-5mol/L) caused a sigmoidal dose-dependent inhibition of endothelial cell migration in the wound scrape model. Fumagillin showed a similar response over a lower dose range (10-13 to 10-9 mol/L); however, the maximal inhibition was less (25% versus 43% for AQ4N). AQ4N inhibited HMEC-1 cell contacts on Matrigel (10-8 to 10-5 mol/L), HMEC-1 cell invasion, and sprouting in rat aorta explants. Immunofluorescence staining with tubulin, vimentim, dynein, and phalloidin revealed that AQ4N caused disruption to the cell cytoskeleton. When AQ4N (20 mg/kg) was given in vivo for 5 days, microvessels disappeared in LNCaP tumors grown in a dorsal skin flap.
Conclusions:This combination of assays has shown that AQ4N possesses antiangiogenic effects in normoxic conditions, which could potentially contribute to antitumor activity
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In this paper a novel scalable public-key processor architecture is presented that supports modular exponentiation and Elliptic Curve Cryptography over both prime GF(p) and binary GF(2) extension fields. This is achieved by a high performance instruction set that provides a comprehensive range of integer and polynomial basis field arithmetic. The instruction set and associated hardware are generic in nature and do not specifically support any cryptographic algorithms or protocols. Firmware within the device is used to efficiently implement complex and data intensive arithmetic. A firmware library has been developed in order to demonstrate support for numerous exponentiation and ECC approaches, such as different coordinate systems and integer recoding methods. The processor has been developed as a high-performance asymmetric cryptography platform in the form of a scalable Verilog RTL core. Various features of the processor may be scaled, such as the pipeline width and local memory subsystem, in order to suit area, speed and power requirements. The processor is evaluated and compares favourably with previous work in terms of performance while offering an unparalleled degree of flexibility. © 2006 IEEE.
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Matrix algorithms are important in many types of applications including image and signal processing. A close examination of the algorithms used in these, and related, applications reveals that many of the fundamental actions involve matrix algorithms such as matrix multiplication. This paper presents an investigation into the design and implementation of different matrix algorithms such as matrix operations, matrix transforms and matrix decompositions using a novel custom coprocessor system for MATrix algorithms based on Reconfigurable Computing (RCMAT). The proposed RCMAT architectures are scalable, modular and require less area and time complexity with reduced latency when compared with existing structures.
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We continue the study of multidimensional operator multipliers initiated in~cite{jtt}. We introduce the notion of the symbol of an operator multiplier. We characterise completely compact operator multipliers in terms of their symbol as well as in terms of approximation by finite rank multipliers. We give sufficient conditions for the sets of compact and completely compact multipliers to coincide and characterise the cases where an operator multiplier in the minimal tensor product of two C*-algebras is automatically compact. We give a description of multilinear modular completely compact completely bounded maps defined on the direct product of finitely many copies of the C*-algebra of compact operators in terms of tensor products, generalising results of Saar
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To date, the processing of wildlife location data has relied on a diversity of software and file formats. Data management and the following spatial and statistical analyses were undertaken in multiple steps, involving many time-consuming importing/exporting phases. Recent technological advancements in tracking systems have made large, continuous, high-frequency datasets of wildlife behavioral data available, such as those derived from the global positioning system (GPS) and other animal-attached sensor devices. These data can be further complemented by a wide range of other information about the animals’ environment. Management of these large and diverse datasets for modelling animal behaviour and ecology can prove challenging, slowing down analysis and increasing the probability of mistakes in data handling. We address these issues by critically evaluating the requirements for good management of GPS data for wildlife biology. We highlight that dedicated data management tools and expertise are needed. We explore current research in wildlife data management. We suggest a general direction of development, based on a modular software architecture with a spatial database at its core, where interoperability, data model design and integration with remote-sensing data sources play an important role in successful GPS data handling.
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The Hoxa9 and Meis1 genes represent important oncogenic collaborators activated in a significant proportion of human leukemias with genetic alterations in the MLL gene. In this study, we show that the transforming property of Meis1 is modulated by 3 conserved domains, namely the Pbx interaction motif (PIM), the homeodomain, and the C-terminal region recently described to possess transactivating properties. Meis1 and Pbx1 interaction domain-swapping mutants are dysfunctional separately, but restore the full oncogenic activity of Meis1 when cotransduced in primary cells engineered to overexpress Hoxa9, thus implying a modular nature for PIM in Meis1-accelerated transformation. Moreover, we show that the transactivating domain of VP16 can restore, and even enhance, the oncogenic potential of the Meis1 mutant lacking the C-terminal 49 amino acids. In contrast to Meis1, the fusion VP16-Meis1 is spontaneously oncogenic, and all leukemias harbor genetic activation of endogenous Hoxa9 and/or Hoxa7, suggesting that Hoxa gene activation represents a key event required for the oncogenic activity of VP16-Meis1.
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As a potential alternative to CMOS technology, QCA provides an interesting paradigm in both communication and computation. However, QCAs unique four-phase clocking scheme and timing constraints present serious timing issues for interconnection and feedback. In this work, a cut-set retiming design procedure is proposed to resolve these QCA timing issues. The proposed design procedure can accommodate QCAs unique characteristics by performing delay-transfer and time-scaling to reallocate the existing delays so as to achieve efficient clocking zone assignment. Cut-set retiming makes it possible to effectively design relatively complex QCA circuits that include feedback. It utilizes the similar characteristics of synchronization, deep pipelines and local interconnections common to both QCA and systolic architectures. As a case study, a systolic Montgomery modular multiplier is designed to illustrate the procedure. Furthermore, a nonsystolic architecture, an S27 benchmark circuit, is designed and compared with previous designs. The comparison shows that the cut-set retiming method achieves a more efficient design, with a reduction of 22%, 44%, and 46% in terms of cell count, area, and latency, respectively.
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A queue manager (QM) is a core traffic management (TM) function used to provide per-flow queuing in access andmetro networks; however current designs have limited scalability. An on-demand QM (OD-QM) which is part of a new modular field-programmable gate-array (FPGA)-based TM is presented that dynamically maps active flows to the available physical resources; its scalability is derived from exploiting the observation that there are only a few hundred active flows in a high speed network. Simulations with real traffic show that it is a scalable, cost-effective approach that enhances per-flow queuing performance, thereby allowing per-flow QM without the need for extra external memory at speeds up to 10 Gbps. It utilizes 2.3%–16.3% of a Xilinx XC5VSX50t FPGA and works at 111 MHz.
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A full hardware implementation of a Weighted Fair Queuing (WFQ) packet scheduler is proposed. The circuit architecture presented has been implemented using Altera Stratix II FPGA technology, utilizing RLDII and QDRII memory components. The circuit can provide fine granularity Quality of Service (QoS) support at a line throughput rate of 12.8Gb/s in its current implementation. The authors suggest that, due to the flexible and scalable modular circuit design approach used, the current circuit architecture can be targeted for a full ASIC implementation to deliver 50 Gb/s throughput. The circuit itself comprises three main components; a WFQ algorithm computation circuit, a tag/time-stamp sort and retrieval circuit, and a high throughput shared buffer. The circuit targets the support of emerging wireline and wireless network nodes that focus on Service Level Agreements (SLA's) and Quality of Experience.
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BACKGROUND: Acute ankle sprains are usually managed functionally, with advice to undertake progressive weight-bearing and walking. Mechanical loading is an important modular of tissue repair; therefore, the clinical effectiveness of walking after ankle sprain may be dose dependent. The intensity, magnitude and duration of load associated with current functional treatments for ankle sprain are unclear.
AIM: To describe physical activity (PA) in the first week after ankle sprain and to compare results with a healthy control group.
METHODS: Participants (16-65 years) with an acute ankle sprain were randomised into two groups (standard or exercise). Both groups were advised to apply ice and compression, and walk within the limits of pain. The exercise group undertook additional therapeutic exercises. PA was measured using an activPAL accelerometer, worn for 7 days after injury. Comparisons were made with a non-injured control group.
RESULTS: The standard group were significantly less active (1.2 ± 0.4 h activity/day; 5621 ± 2294 steps/day) than the exercise (1.7 ± 0 .7 h/day, p=0.04; 7886 ± 3075 steps/day, p=0.03) and non-injured control groups (1.7 ± 0.4 h/day, p=0.02; 8844 ± 2185 steps/day, p=0.002). Also, compared with the non-injured control group, the standard and exercise groups spent less time in moderate (38.3 ± 12.7 min/day vs 14.5 ± 11.4 min/day, p=0.001 and 22.5 ± 15.9 min/day, p=0.003) and high-intensity activity (4.1 ± 6.9 min/day vs 0.1 ± 0.1 min/day, p=0.001 and 0.62 ± 1.0 min/day p=0.005).
CONCLUSION: PA patterns are reduced in the first week after ankle sprain, which is partly ameliorated with addition of therapeutic exercises. This study represents the first step towards developing evidence-based walking prescription after acute ankle sprain.
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Methods are presented for developing synthesizable FFT cores. These are based on a modular approach in which parameterized commutator and processor blocks are cascaded to implement the computations required in many important FFT signal flow graphs. In addition, it is shown how the use of a digital serial data organization can be used to produce systems that offer 100% processor utilization along with reductions in storage requirements. The approach has been used to create generators for the automated synthesis of FFT cores that are portable across a broad range of silicon technologies. Resulting chip designs are competitive with ones created using manual methods but with significant reductions in design times.
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A novel hardware architecture for elliptic curve cryptography (ECC) over GF(p) is introduced. This can perform the main prime field arithmetic functions needed in these cryptosystems including modular inversion and multiplication. This is based on a new unified modular inversion algorithm that offers considerable improvement over previous ECC techniques that use Fermat's Little Theorem for this operation. The processor described uses a full-word multiplier which requires much fewer clock cycles than previous methods, while still maintaining a competitive critical path delay. The benefits of the approach have been demonstrated by utilizing these techniques to create a field-programmable gate array (FPGA) design. This can perform a 256-bit prime field scalar point multiplication in 3.86 ms, the fastest FPGA time reported to date. The ECC architecture described can also perform four different types of modular inversion, making it suitable for use in many different ECC applications. © 2006 IEEE.
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A methodology has been developed which allows a non-specialist to rapidly design silicon wavelet transform cores for a variety of specifications. The cores include both forward and inverse orthonormal wavelet transforms. This methodology is based on efficient, modular and scaleable architectures utilising time-interleaved coefficients for the wavelet transform filters. The cores are parameterized in terms of wavelet type and data and coefficient word lengths. The designs have been captured in VHDL and are hence portable across a range of silicon foundries as well as FPGA and PLD implementations.
Resumo:
Methods are presented for developing synthesizable FFT cores. These are based on a modular approach in which parameterizable blocks are cascaded to implement the computations required across a range of typical FFT signal flow graphs. The underlying architectural approach combines the use of a digital serial data organization with generic commutator blocks to produce systems that offer 100% processor utilization with storage requirements less than previous designs. The approach has been used to create generators for the automated synthesis of FFT cores that are portable across a broad range of silicon technologies. Resulting chip designs are competitive with manual methods but with significant reductions in design times.
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A full-scale 34 m composite wind turbine blade was tested to failure under flap-wise loading. Local displacement measurement equipment was developed and displacements were recorded throughout the loading history.
Ovalization of the load carrying box girder was measured in the full-scale test and simulated in non-linear FE-calculations. The nonlinear Brazier effect is characterized by a crushing pressure which causes the ovalization. To capture this effect, non-linear FE-analyses at different scales were employed. A global non-linear FE-model of the entire blade was prepared and the boundaries to a more detailed sub-model were extracted. The FE-model was calibrated based on full-scale test measurements.
Local displacement measurements helped identify the location of failure initiation which lead to catastrophic failure. Comparisons between measurements and FE-simulations showed that delamination of the outer skin was the initial failure mechanism followed by delamnination buckling which then led to collapse.