Understanding the dehydrogenation mechanism of tetrahydrocarbazole over palladium using a combined experimental and density functional theory approach

The mechanism of the dehydrogenation of tetrahydrocarbazole to carbazole over palladium has been examined for the first time. By use of a combination of deuterium exchange experiments and density functional theory calculations, a detailed reaction profile for the aromatization of tetrahydrocarbazole has been identified and validated by experiment. As with many dehydrogenation reactions, the initial hydrogen abstraction is found to have the highest reaction barrier. Tetrahydrocarbazole has four hydrogens which can, in principle, be cleaved initially; however, the theory and experiment show that the reaction is dominated by the cleavage of the carbon hydrogens at the carbon atoms in positions 1 and 4. The two pathways originating from these two C-H bond cleavage processes are found to have similar reaction energy profiles and both contribute to the overall reaction.

Electrochemical synthesis and characterization of conducting polymers using room temperature melt as an electrolyte

Aromatic monomers can be polymerised using the chloroaluminate room temperature melt obtained by mixing 1:2 ratio of cetyl pyridinium chloride and anhydrous aluminium chloride miscible in all proportions with organic solvents as an electrolyte. The chloroaluminate (AlCl4-) anion generated in this melt having a tetrahedral symmetry with equal bond lengths and bond angles is the dopant to stabilize macrocation generated near the vicinity of anode to yield better conducting and better ordered electronically conducting free standing polymer film. In this communication, we discuss the polymers derived from benzene and pyrrole and their characterization by various techniques.

Electrochemical synthesis and characterization of conducting polyparaphenylene using room-temperature melt as the electrolyte

Freestanding polyparaphenylene films were obtained on polymerization of benzene at potential of 1.2 V versus Al wire on substrates like platinum/transparent conducting glass as an anode. The electrolyte used was chloroaluminate room-temperature melt, which was prepared by intimate mixing of a 1:2 ratio of cetyl pyridinium chloride and anhydrous aluminum chloride to yield a viscous liquid. This liquid was miscible in all proportions with benzene and other aromatic hydrocarbons in all proportions at room temperature. The polyparaphenylene films deposited on platinum anode exhibited a prominent cyclic voltammetric peak at 0.7 V versus Al wire as reference electrode in chloroaluminate medium. The impedance spectra gave low charge transfer resistance. The diffused reflectance electronic spectra of the film gave the peaks at 386 nm and 886 nm. The PPP films showed electronic conductivity around 3–4 × 104 S/cm by four probe method under nitrogen atmosphere. The polymer was also characterized by IR spectra, thermal studies, and SEM studies.

Synthesis, characterization and temperature studies on the conductivity of AlCl−4 ion doped polypyrrole

Synthesis of free standing conducting polypyrrole film using room temperature melt as the electrolyte is reported. We also report variation in the contribution of ionic conductance with temperature of the polymer film by four probe method and electrochemical properties like diffusion coefficient and ionic mobility of AlCl-4 doped polypyrrole film. An attempt has been made to arrive at the stability of charge carrier concentration over a temperature range of 295 to 350 K under vacuum. The film was characterized by optical techniques and scanning electron micrography.

Magnetic tight binding and the iron-chromium enthalpy anomaly

We describe a self-consistent magnetic tight-binding theory based in an expansion of the Hohenberg-Kohn density functional to second order, about a non-spin-polarized reference density. We show how a first order expansion about a density having a trial input magnetic moment leads to a fixed moment model. We employ a simple set of tight-binding parameters that accurately describes electronic structure and energetics, and show these to be transferable between first row transition metals and their alloys. We make a number of calculations of the electronic structure of dilute Cr impurities in Fe, which we compare with results using the local spin density approximation. The fixed moment model provides a powerful means for interpreting complex magnetic configurations in alloys; using this approach, we are able to advance a simple and readily understood explanation for the observed anomaly in the enthalpy of mixing.

Characteristics of the interfacial capacitance in thin film Ba0.5Sr0.5TiO3 capacitors with SrRuO3 and (La, Sr)CoO3 bottom electrodes

Thin film Ba0.5Sr0.5TiO3 (BST) capacitors of thickness similar to75 nm to similar to1200 nm, with Au top electrodes and SrRuO 3 (SRO) or (La, Sr)CoO3 (LSCO) bottom electrodes were fabricated using Pulsed Laser Deposition. Implementing the "series capacitor model," bulk and interfacial capacitance properties were extracted as a function of temperature and frequency. 'Bulk' properties demonstrated typical ceramic behaviour, displaying little frequency dependence and a permittivity and loss peak at 250 K and 150 K respectively. The interfacial component was found to be relatively temperature and frequency independent for the LSCO/BST capacitors, but for the SRO/BST configuration the interfacial capacitance demonstrated moderate frequency and little temperature dependence below T similar to 300 K but a relatively strong frequency and temperature dependence above T similar to3 00 K. This was attributed to the thermal activation of a space charge component combined with a thermally independent background. The activation energy for the space charge was found to be E-A similar to 0.6 eV suggesting de-trapping of electrons from shallow level traps associated with a thin interfacial layer of oxygen vacancies, parallel to the electrodes.

Progressive loss of ferroelectricity under bipolar pulsed fields and experimental determination of non-switchable polarization in Au/Ba0.5Sr0.5TiO3/SrRuO3 thin-film capacitors

175 nm-thick Ba0.5Sr0.5TiO3 (BST) thin film fabricated by pulsed laser deposition (PLD) technique is found to be a mixture of two distributions of material. We discuss whether these two components are nano-regions of paraelectric and ferroelectric phases, or a bimodal grain-size distribution, or an effect of oxygen vacancy gradient from the electrode interface. The fraction of switchable ferroelectric phase decreases under bipolar pulsed fields, but it recovers after removal of the external fields. The plot of capacitance in decreasing dc voltage (C(Vdown arrow) versus that in increasing dc 61 voltage C(Vup arrow) is a superposition of overlapping of two triangles, in contrast to one well-defined triangle for typical ferroelectric SrBi2Ta2O9 thin films.

6-T SRAM cell design with nanoscale double-gate SOI MOSFETs: impact of source/drain engineering and circuit topology

The impact of source/drain engineering on the performance of a six-transistor (6-T) static random access memory (SRAM) cell, based on 22 nm double-gate (DG) SOI MOSFETs, has been analyzed using mixed-mode simulation, for three different circuit topologies for low voltage operation. The trade-offs associated with the various conflicting requirements relating to read/write/standby operations have been evaluated comprehensively in terms of eight performance metrics, namely retention noise margin, static noise margin, static voltage/current noise margin, write-ability current, write trip voltage/current and leakage current. Optimal design parameters with gate-underlap architecture have been identified to enhance the overall SRAM performance, and the influence of parasitic source/drain resistance and supply voltage scaling has been investigated. A gate-underlap device designed with a spacer-to-straggle (s/sigma) ratio in the range 2-3 yields improved SRAM performance metrics, regardless of circuit topology. An optimal two word-line double-gate SOI 6-T SRAM cell design exhibits a high SNM similar to 162 mV, I-wr similar to 35 mu A and low I-leak similar to 70 pA at V-DD = 0.6 V, while maintaining SNM similar to 30% V-DD over the supply voltage (V-DD) range of 0.4-0.9 V.

Performance projections and design optimization of planar double gate SOI MOSFETs for logic technology applications

In this paper, by investigating the influence of source/drain extension region engineering (also known as gate-source/drain underlap) in nanoscale planar double gate (DG) SOI MOSFETs, we offer new insights into the design of future nanoscale gate-underlap DG devices to achieve ITRS projections for high performance (HP), low standby power (LSTP) and low operating power (LOP) logic technologies. The impact of high-kappa gate dielectric, silicon film thickness, together with parameters associated with the lateral source/drain doping profile, is investigated in detail. The results show that spacer width along with lateral straggle can not only effectively control short-channel effects, thus presenting low off-current in a gate underlap device, but can also be optimized to achieve lower intrinsic delay and higher on-off current ratio (I-on/I-off). Based on the investigation of on-current (I-on), off-current (I-off), I-on/I-off, intrinsic delay (tau), energy delay product and static power dissipation, we present design guidelines to select key device parameters to achieve ITRS projections. Using nominal gate lengths for different technologies, as recommended from ITRS specification, optimally designed gate-underlap DG MOSFETs with a spacer-to-straggle (s/sigma) ratio of 2.3 for HP/LOP and 3.2 for LSTP logic technologies will meet ITRS projection. However, a relatively narrow range of lateral straggle lying between 7 to 8 nm is recommended. A sensitivity analysis of intrinsic delay, on-current and off-current to important parameters allows a comparative analysis of the various design options and shows that gate workfunction appears to be the most crucial parameter in the design of DG devices for all three technologies. The impact of back gate misalignment on I-on, I-off and tau is also investigated for optimized underlap devices.

The impact of the intrinsic and extrinsic resistances of double gate SOI on RF performance

In this paper, the analogue performance of a 65 nm node double gate Sol (DGSOI) is qualitatively investigated using MixedMode simulation. The intrinsic resistance of the device is optimised by evaluating the impact of the source/drain engineering using variation of spacers and doping profile on the RF key figures of merit such as f(T), and f(MAX). It is evident that longer spacers, which approach the length of the gate offer better RF performance irrespective of the profile as long as the doping gradient at the gate edge is <7 nm/decade. Analytical expressions, which reflect the dependence of f(T), and fMAX on extrinsic source, drain and gate resistances R-S, R-D and R-G have been derived. While R-D and R-S have equal effect on f(T), R-D appears to be more influential than R-S in reducing f(MAX). The sensitivity of f(MAX) to R-S and R-D. has been shown to be greater than to R-G. (c) 2006 Elsevier Ltd. All rights reserved.

Engineering source/drain extension regions in nanoscale double gate (DG) SOI MOSFETs: Analytical model and design considerations

In this paper, we propose for the first time, an analytical model for short channel effects in nanoscale source/drain extension region engineered double gate (DG) SOI MOSFETs. The impact of (i) lateral source/drain doping gradient (d), (ii) spacer width (s), (iii) spacer to doping gradient ratio (s/d) and (iv) silicon film thickness (T-si), on short channel effects - threshold voltage (V-th) and subthreshold slope (S), on-current (I-on), off-current (I-on) and I-on/I-off is extensively analysed by using the analytical model and 2D device simulations. The results of the analytical model confirm well with simulated data over the entire range of spacer widths, doping gradients and effective channel lengths. Results show that lateral source/drain doping gradient along with spacer width can not only effectively control short channel effects, thus presenting low off-current, but can also be optimised to achieve high values of on-currents. The present work provides valuable design insights in the performance of nanoscale DG Sol devices with optimal source/drain engineering and serves as a tool to optimise important device and technological parameters for 65 nm technology node and below. (c) 2006 Elsevier Ltd. All rights reserved.

Extrinsic parameter extraction and RF modelling of CMOS

An analytical approach for CMOS parameter extraction which includes the effect of parasitic resistance is presented. The method is based on small-signal equivalent circuit valid in all region of operation to uniquely extract extrinsic resistances, which can be used to extend the industry standard BSIM3v3 MOSFET model for radio frequency applications. The verification of the model was carried out through frequency domain measurements of S-parameters and direct time domain measurement at 2.4 GHz in a large signal non-linear mode of operation. (C) 2003 Elsevier Ltd. All rights reserved.

Electrochemical reduction of benzoic acid and substituted benzoic acids in some room temperature ionic liquids

Using cyclic voltammetry, the electrochemical reduction of benzoic acid (BZA) has been studied at Pt and Au microelectrodes (10 and 2 mu m diameter) in six room temperature ionic liquids (RTILs), namely [C(2)mim][NTf2], [C(4)mim][NTf2], [C(4)mpyrr][NTf2], [C(4)mim][BF4], [C(4)mim][NO3], and [C(4)mim][PF6] (where [C(n)mim](+) = 1-alkyl-3-methylimidazolium, [NTf2](-) = bis(trifluoromethylsulfonyl)imide, [C(4)mpyrr](+) = N-butyl-N-methylpyrrolidinium, [BF4](-) = tetrafluoroborate, [NO3](-) = nitrate, and [PF6](-) = hexafluorophosphate). In all cases, a main reduction peak was observed, assigned to the reduction of BZA in a CE mechanism, where dissociation of the acid takes place before electron transfer to the dissociated proton. One anodic peak was observed on the reverse sweep, assigned to the oxidation of adsorbed hydrogen, and a reductive

Modulating the selectivity for CO and butane oxidation over heterogeneous catalysis through amorphous catalyst coatings

The preparation of porous films directly deposited onto the surface of catalyst particles is attracting increasing attention. We report here for the first time a method that can be carried out at ambient pressure for the preparation of porous films deposited over 3 mm diameter catalyst particles of silica-supported Pt-Fe. Characterization of the sample prepared at ambient pressure (i.e., open air, OA) and its main structural differences as compared with a Na-A (LTA) coated catalyst made using an autoclave-based method are presented. The OA-coated material predominantly exhibited an amorphous film over the catalyst surface with between 4 and 13% of crystallinity as compared with fully crystallized LTA zeolite crystals. This coated sample was highly selective for CO oxidation in the presence of butane with no butane oxidation observed up to 350 degrees C. This indicates, for the first time, that the presence of a crystalline membrane is not necessary for the difference in light off temperature between CO and butane to be achieved and that amorphous films may also produce this effect. An examination of the space velocity dependence and adsorption of Na+ on the catalysts indicates that the variation in CO and butane oxidation activity is not caused by site blocking predominantly, although the Pt activity was lowered by contact with this alkali.

Electrode kinetics and mechanism of iodine reduction in the room-temperature ionic liquid [C(4)mim][NTf2]

The fast electrochemical reduction of iodine in the RTIL 1-butyl-3-methylimidazolium bis(trifluoromethyl-sulfonyl)imide, [C(4)mim][NTf2], is reported and the kinetics and mechanism of the process elucidated. Two reduction peaks were observed. The first reduction peak is assigned to the process