Cartographic veracity in medieval mapping: analyzing geographical variation in the Gough Map of Great Britain

This article explores statistical approaches for assessing the relative accuracy of medieval mapping. It focuses on one particular map, the Gough Map of Great Britain. This is an early and remarkable example of a medieval “national” map covering Plantagenet Britain. Conventionally dated to c. 1360, the map shows the position of places in and coastal outline of Great Britain to a considerable degree of spatial accuracy. In this article, aspects of the map's content are subjected to a systematic analysis to identify geographical variations in the map's veracity, or truthfulness. It thus contributes to debates among historical geographers and cartographic historians on the nature of medieval maps and mapping and, in particular, questions of their distortion of geographic space. Based on a newly developed digital version of the Gough Map, several regression-based approaches are used here to explore the degree and nature of spatial distortion in the Gough Map. This demonstrates that not only are there marked variations in the positional accuracy of places shown on the map between regions (i.e., England, Scotland, and Wales), but there are also fine-scale geographical variations in the spatial accuracy of the map within these regions. The article concludes by suggesting that the map was constructed using a range of sources, and that the Gough Map is a composite of multiscale representations of places in Great Britain. The article details a set of approaches that could be transferred to other contexts and add value to historic maps by enhancing understanding of their contents.

A recursive rule base adjustment algorithm for a fuzzy logic controller

This paper introduces a recursive rule base adjustment to enhance the performance of fuzzy logic controllers. Here the fuzzy controller is constructed on the basis of a decision table (DT), relying on membership functions and fuzzy rules that incorporate heuristic knowledge and operator experience. If the controller performance is not satisfactory, it has previously been suggested that the rule base be altered by combined tuning of membership functions and controller scaling factors. The alternative approach proposed here entails alteration of the fuzzy rule base. The recursive rule base adjustment algorithm proposed in this paper has the benefit that it is computationally more efficient for the generation of a DT, and advantage for online realization. Simulation results are presented to support this thesis. (c) 2005 Elsevier B.V. All rights reserved.

Performance projections and design optimization of planar double gate SOI MOSFETs for logic technology applications

In this paper, by investigating the influence of source/drain extension region engineering (also known as gate-source/drain underlap) in nanoscale planar double gate (DG) SOI MOSFETs, we offer new insights into the design of future nanoscale gate-underlap DG devices to achieve ITRS projections for high performance (HP), low standby power (LSTP) and low operating power (LOP) logic technologies. The impact of high-kappa gate dielectric, silicon film thickness, together with parameters associated with the lateral source/drain doping profile, is investigated in detail. The results show that spacer width along with lateral straggle can not only effectively control short-channel effects, thus presenting low off-current in a gate underlap device, but can also be optimized to achieve lower intrinsic delay and higher on-off current ratio (I-on/I-off). Based on the investigation of on-current (I-on), off-current (I-off), I-on/I-off, intrinsic delay (tau), energy delay product and static power dissipation, we present design guidelines to select key device parameters to achieve ITRS projections. Using nominal gate lengths for different technologies, as recommended from ITRS specification, optimally designed gate-underlap DG MOSFETs with a spacer-to-straggle (s/sigma) ratio of 2.3 for HP/LOP and 3.2 for LSTP logic technologies will meet ITRS projection. However, a relatively narrow range of lateral straggle lying between 7 to 8 nm is recommended. A sensitivity analysis of intrinsic delay, on-current and off-current to important parameters allows a comparative analysis of the various design options and shows that gate workfunction appears to be the most crucial parameter in the design of DG devices for all three technologies. The impact of back gate misalignment on I-on, I-off and tau is also investigated for optimized underlap devices.