Linear QR architecture for a single chip adaptive beamformer

This paper presents the design of a novel single chip adaptive beamformer capable of performing 50 Gflops, (Giga-floating-point operations/second). The core processor is a QR array implemented on a fully efficient linear systolic architecture, derived using a mapping that allows individual processors for boundary and internal cell operations. In addition, the paper highlights a number of rapid design techniques that have been used to realise this system. These include an architecture synthesis tool for quickly developing the circuit architecture and the utilisation of a library of parameterisable silicon intellectual property (IP) cores, to rapidly develop detailed silicon designs.

Electronic cell counting to measure total cell numbers in bronchoalveolar lavage fluid

Cell counting of bronchoalveolar lavage (BAL) fluid is performed manually in routine practice. This has both methodological and inherent errors; however, the accuracy and suitability of automated counting devices have been questioned. In this study, a Coulter(R) Counter D Industrial model was calibrated and then used to measure the total cell count in unprocessed bronchoalveolar lavage fluid, and compared to a standard manual method.

Reconfigurable system-on-a-chip motion estimation architecture for multi-standard video coding

A new domain-specific, reconfigurable system-on-a-chip (SoC) architecture is proposed for video motion estimation. This has been designed to cover most of the common block-based video coding standards, including MPEG-2, MPEG-4, H.264, WMV-9 and AVS. The architecture exhibits simple control, high throughput and relatively low hardware cost when compared with existing circuits. It can also easily handle flexible search ranges without any increase in silicon area and can be configured prior to the start of the motion estimation process for a specific standard. The computational rates achieved make the circuit suitable for high-end video processing applications, such as HDTV. Silicon design studies indicate that circuits based on this approach incur only a relatively small penalty in terms of power dissipation and silicon area when compared with implementations for specific standards. Indeed, the cost/performance achieved exceeds that of existing but specific solutions and greatly exceeds that of general purpose field programmable gate array (FPGA) designs.

Chip design for high-performance DSP

Advances in silicon technology have been a key development in the realisation of many telecommunication and signal processing systems. In many cases, the development of application-specific digital signal processing (DSP) chips is the most cost-effective solution and provides the highest performance. Advances made in computer-aided design (CAD) tools and design methodologies now allow designers to develop complex chips within months or even weeks. This paper gives an insight into the challenges and design methodologies of implementing advanced highperformance chips for DSP. In particular, the paper reviews some of the techniques used to develop circuit architectures from high-level descriptions and the tools which are then used to realise silicon layout.

Phenomenology and system engineering of micro- and nano-antenna FPA sensors for detection of concealed weapons and improvised explosive devices

The ability of millimetre wave and terahertz systems to penetrate clothing is well known. The fact that the transmission of clothing and the reflectivity of the body vary as a function of frequency is less so. Several instruments have now been developed to exploit this capability. The choice of operating frequency, however, has often been associated with the maturity and the cost of the enabling technology rather than a sound systems engineering approach. Top level user and systems requirements have been derived to inform the development of design concepts. Emerging micro and nano technology concepts have been reviewed and we have demonstrated how these can be evaluated against these requirements by simulation using OpenFx. Openfx is an open source suite of 3D tools for modeling, animation and visualization which has been modified for use at millimeter waves. © 2012 SPIE.

Optical Cooling of Atoms in Microtraps by Time-Delayed Reflection

We present a theoretical analysis of a novel scheme for optical cooling of particles that does not in principle require a closed optical transition. A tightly confined laser beam interacting with a trapped particle experiences a phase shift, which upon reflection from a mirror or resonant microstructure produces a time-delayed optical potential for the particle. This leads to a nonconservative force and friction. A quantum model of the system is presented and analyzed in the semiclassical limit.

JPEG encoder system-on-a-chip demonstrator

The design of a System-on-a-Chip (SoC) demonstrator for a baseline JPEG encoder core is presented. This combines a highly optimized Discrete Cosine Transform (DCT) and quantization unit with an entropy coder which has been realized using off-the-shelf synthesizable IP cores (Run-length coder, Huffman coder and data packer). When synthesized in a 0.35 µm CMOS process, the core can operate at speeds up to 100 MHz and contains 50 k gates plus 11.5 kbits of RAM. This is approximately 20% less than similar JPEG encoder designs reported in literature. When targeted at FPGA the core can operate up to 30 MHz and is capable of compressing 9-bit full-frame color input data at NTSC or PAL rates.

New FFT architecture and chip design for motion compensation based on phase correlation

Details of a new low power FFT processor for use in digital television applications are presented. This has been fabricated using a 0.6 µm CMOS technology and can perform a 64 point complex forward or inverse FFT on real-rime video at up to 18 Megasamples per second. It comprises 0.5 million transistors in a die area of 7.8×8 mm and dissipates 1 W. Its performance, in terms of computational rate per area per watt, is significantly higher than previously reported devices, leading to a cost-effective silicon solution for high quality video processing applications. This is the result of using a novel VLSI architecture which has been derived from a first principles factorisation of the DFT matrix and tailored to a direct silicon implementation.

Wavelet packet transforms for system-on-chip applications

A methodology for the production of silicon cores for wavelet packet decomposition has been developed. The scheme utilizes efficient scalable architectures for both orthonormal and biorthogonal wavelet transforms. The cores produced from these architectures can be readily scaled for any wavelet function and are easily configurable for any subband structure. The cores are fully parameterized in terms of wavelet choice and appropriate wordlengths. Designs produced are portable across a range of silicon foundries as well as FPGA and PLD technologies. A number of exemplar implementations have been produced.

Design of interlock-free combined allocators for Networks-on-Chip

This paper presents a thorough investigation of the combined allocator design for Networks-on-Chip (NoC). Particularly, we discuss the interlock of the combined NoC allocator, which is caused by the lock mechanism of priority updating between the local and global arbiters. Architectures and implementations of three interlock-free combined allocators are presented in detail. Their cost, critical path, as well as network level performance are demonstrated based on 65-nm standard cell technology.

A Trip from a Tube to a Chip Applied Micro and Nanotechnology in Biotechnology, Veterinary and Life Sciences

More than 200 known diseases are transmitted via foods or food products. In the United States, food-borne diseases are responsible for 76 million cases of illness, 32,500 cases of hospitalisation and 5000 cases of death yearly. The ongoing increase in worldwide trade in livestock, food, and food products in combination with increase in human mobility (business- and leisure travel, emigration etc.) will increase the risk of emergence and spreading of such pathogens. There is therefore an urgent need for development of rapid, efficient and reliable methods for detection and identification of such pathogens.

Microchipfabrication has had a major impact on electronics and is expected to have an equally pronounced effect on life sciences. By combining micro-fluidics with micromechanics, micro-optics, and microelectronics, systems can be realized to perform complete chemical or biochemical analyses. These socalled ’Lab-on-a-Chip’ will completely change the face of laboratories in the future where smaller, fully automated devices will be able to perform assays faster, more accurately, and at a lower cost than equipment of today. A general introduction of food safety and applied micro-nanotechnology in life sciences will be given. In addition, examples of DNA micro arrays, micro fabricated integrated PCR chips and total integrated lab-on-achip systems from different National and EU research projects being carried out at the Laboratory of Applied Micro- Nanotechnology (LAMINATE) group at the National Veterinary Institute (DTU-Vet) Technical University of Denmark and the BioLabchip group at the Department of Micro and Nanotechnology (DTU-Nanotech), Technical University of Denmark (DTU), Ikerlan-IK4 (Spain) and other 16 partners from different European countries will be presented.

Voltage over-scaling:A cross-layer design perspective for energy efficient systems

Today's multi-media electronic era is driven by the increasing demand for small multifunctional devices able to support diverse services. Unfortunately, the high levels of transistor integration and performance required by such devices lead to an unprecedented increase of on-chip power that significantly limits the battery lifetime and even poses reliability concerns. Several techniques have been developed to address the power increase, but voltage over-scaling (VOS) is considered to be one of the most effective ones due to the quadratic dependence of voltage on dynamic power consumption. However, VOS may not always be applicable since it increases the delay in all paths of a system and may limit high performance required by today's complex applications. In addition, application of VOS is further complicated since it increases the variations in transistor characteristics imposed by their tiny size which can lead to large delay and leakage variations, making it difficult to meet delay and power budgets. This paper presents a review of various cross-layer design options that can provide solutions for dynamic voltage over-scaling and can potentially assist in meeting the strict power budgets and yield/quality requirements of future systems. © 2011 IEEE.