An ESPRIT-SAA-Based Detection Method for Broken Rotor Bar Fault in Induction Motors

This paper presents a novel detection method for broken rotor bar fault (BRB) in induction motors based on Estimation of Signal Parameters via Rotational Invariance Technique (ESPRIT) and Simulated Annealing Algorithm (SAA). The performance of ESPRIT is tested with simulated stator current signal of an induction motor with BRB. It shows that even with a short-time measurement data, the technique is capable of correctly identifying the frequencies of the BRB characteristic components but with a low accuracy on the amplitudes and initial phases of those components. SAA is then used to determine their amplitudes and initial phases and shows satisfactory results. Finally, experiments on a 3kW, 380V, 50Hz induction motor are conducted to demonstrate the effectiveness of the ESPRIT-SAA-based method in detecting BRB with short-time measurement data. It proves that the proposed method is a promising choice for BRB detection in induction motors operating with small slip and fluctuant load.

FAULT-TOLERANT ALGORITHM FOR HIGH-AVAILABILITY AND WAFER SCALE SYSTEMS.

In this paper, the authors have presented one approach to configuring a Wafer-Scale Integration Chip. The approach described is called the 'WINNER', in which bus channels and an external controller for configuring the working processors are not required. In addition, the technique is applicable to high availability systems constructed using conventional methods. The technique can also be extended to arrays of arbitrary size and with any degree of fault tolerance simply by using an appropriate number of cells.

YIELD ENHANCEMENT OF BIT LEVEL SYSTOLIC ARRAY CHIPS USING FAULT TOLERANT TECHNIQUES.

Methods by which bit level systolic array chips can be made fault tolerant are discussed briefly. Using a simple analysis based on both Poisson and Bose-Einstein statistics authors demonstrate that such techniques can be used to obtain significant yield enhancement. Alternatively, the dimensions of an array can be increased considerably for the same initial (nonfault tolerant) chip yield.

Fault Diagnostics for Internal Combustion Engines – Current and Future Techniques

The adoption of each new level of automotive emissions legislation often requires the introduction of additional emissions reduction techniques or the development of existing emissions control systems. This, in turn, usually requires the implementation of new sensors and hardware which must subsequently be monitored by the on-board fault detection systems. The reliable detection and diagnosis of faults in these systems or sensors, which result in the tailpipe emissions rising above the progressively lower failure thresholds, provides enormous challenges for OBD engineers. This paper gives a review of the field of fault detection and diagnostics as used in the automotive industry. Previous work is discussed and particular emphasis is placed on the various strategies and techniques employed. Methodologies such as state estimation, parity equations and parameter estimation are explained with their application within a physical model diagnostic structure. The utilization of symptoms and residuals in the diagnostic process is also discussed. These traditional physical model based diagnostics are investigated in terms of their limitations. The requirements from the OBD legislation are also addressed. Additionally, novel diagnostic techniques, such as principal component analysis (PCA) are also presented as a potential method of achieving the monitoring requirements of current and future OBD legislation.

Fault Location on a Distribution Network Using a Decentralised Analysis Process

A reduction in the time required to locate and restore faults on a utility's distribution network improves the customer minutes lost (CML) measurement and hence brings direct cost savings to the operating company. The traditional approach to fault location involves fault impedance determination from high volume waveform files dispatched across a communications channel to a central location for processing and analysis. This paper examines an alternative scheme where data processing is undertaken locally within a recording instrument thus reducing the volume of data to be transmitted. Processed event fault reports may be emailed to relevant operational staff for the timely repair and restoration of the line.

Quantitative Analysis of Fault and Fracture Systems and their Impact on Groundwater Flow in Irish Bedrock Aquifers

Fault and fracture systems are the most important store and pathway for groundwater in Ireland’s bedrock aquifers, either directly as conductive flow structures, or indirectly as the locus for the development of dolomitised limestone and karst. This article presents the preliminary results of a study involving the quantitative analysis of fault and fracture systems in the broad range of Irish bedrock types and a consideration of their impact on groundwater flow. The principal aims of the project are to develop generic conceptual models for different fault/fracture systems in different lithologies and at different depths, and to link them to observed groundwater behaviour. Here we briefly describe the geometrical characteristics of the main post-Devonian fault/fracture systems controlling groundwater flow from field observations at outcrops, quarries and mines. The structures range from Lower Carboniferous normal faults through to Variscan-related faults and veins, with the most recent structures including Tertiary strike-slip faults and ubiquitous uplift-related joint systems. The geometrical characteristics of different fault/fracture systems combined with observations of groundwater behaviour in both quarry and mine localities, can be linked to general flow and transport conceptualisations of Irish fractured bedrock. Most importantly they also provide a basis for relating groundwater flow to particular fault/fracture systems and their expression with depth and within different lithological sequences, as well as their regional variability.

Pre-charging and DC Fault Ride-Through of Hybri MMC Based HVDC Systems

Compared to half-bridge based MMCs, full-bridge based systems have the advantage of blocking dc fault, but at the expense of increased power semiconductors and power losses. In view of the relationships among ac/dc voltages and currents in full-bridge based MMC with the negative voltage state, this paper provides a detailed analysis on the link between capacitor voltage variation and the maximum modulation index. A hybrid MMC, consisting of mixed half-bridge and full-bridge circuits to combine their respective advantages is investigated in terms of its pre-charging process and transient dc fault ride-through capability. Simulation and experiment results demonstrate the feasibility and validity of the proposed strategy for a full-bridge based MMC and the hybrid MMC.

Analysis of voltage source converter-based high-voltage direct current under DC line-to-earth fault

DC line faults on high-voltage direct current (HVDC) systems utilising voltage source converters (VSCs) are a major issue for multi-terminal HVDC systems in which complete isolation of the faulted system is not a viable option. Of these faults, single line-to-earth faults are the most common fault scenario. To better understand the system under such faults, this study analyses the behaviour of HVDC systems based on both conventional two-level converter and multilevel modular converter technology, experiencing a permanent line-to-earth fault. Operation of the proposed system under two different earthing configurations of converter side AC transformer earthed with converter unearthed, and both converter and AC transformer unearthed, was analysed and simulated, with particular attention paid to the converter operation. It was observed that the development of potential earth loops within the system as a result of DC line-to-earth faults leads to substantial overcurrent and results in oscillations depending on the earthing configuration.

Flexible fault ride through strategy for wind farm clusters in power systems with high wind power penetration

This paper investigates a flexible fault ride through strategy for power systems in China with high wind power penetration. The strategy comprises of adaptive fault ride through requirements and maximum power restrictions of the wind farms with weak fault ride through capabilities. The slight faults and moderate faults with high probability are the main defending objective of the strategy. The adaptive fault ride through requirement in the strategy consists of two sub fault ride through requirements, a temporary slight voltage ride through requirement corresponding to a slight fault incident, with a moderate voltage ride through requirement corresponding to a moderate fault. The temporary overloading capability of the wind farm is reflected in both requirements to enhance the capability to defend slight faults and to avoid tripping when the crowbar is disconnected after moderate faults are cleared. For those wind farms that cannot meet the adaptive fault ride through requirement, restrictions are put on the maximum power output. Simulation results show that the flexible fault ride through strategy increases the fault ride through capability of the wind farm clusters and reduces the wind power curtailment during faults.

Performance and Fault Tolerance of Preconditioned Iterative Solvers on Low-Power ARM Architectures

As the complexity of computing systems grows, reliability and energy are two crucial challenges asking for holistic solutions. In this paper, we investigate the interplay among concurrency, power dissipation, energy consumption and voltage-frequency scaling for a key numerical kernel for the solution of sparse linear systems. Concretely, we leverage a task-parallel implementation of the Conjugate Gradient method, equipped with an state-of-the-art pre-conditioner embedded in the ILUPACK software, and target a low-power multi core processor from ARM.In addition, we perform a theoretical analysis on the impact of a technique like Near Threshold Voltage Computing (NTVC) from the points of view of increased hardware concurrency and error rate.

Evaluating fault tolerance on asymmetric multicore systems-on-chip using iso-metrics

The end of Dennard scaling has promoted low power consumption into a firstorder concern for computing systems. However, conventional power conservation schemes such as voltage and frequency scaling are reaching their limits when used in performance-constrained environments. New technologies are required to break the power wall while sustaining performance on future processors. Low-power embedded processors and near-threshold voltage computing (NTVC) have been proposed as viable solutions to tackle the power wall in future computing systems. Unfortunately, these technologies may also compromise per-core performance and, in the case of NTVC, xreliability. These limitations would make them unsuitable for HPC systems and datacenters. In order to demonstrate that emerging low-power processing technologies can effectively replace conventional technologies, this study relies on ARM’s big.LITTLE processors as both an actual and emulation platform, and state-of-the-art implementations of the CG solver. For NTVC in particular, the paper describes how efficient algorithm-based fault tolerance schemes preserve the power and energy benefits of very low voltage operation.