Area-efficient high-speed 3D DWT processor architecture

An area-efficient high-throughput architecture based on distributed arithmetic is proposed for 3D discrete wavelet transform (DWT). The 3D DWT processor was designed in VHDL and mapped to a Xilinx Virtex-E FPGA. The processor runs up to 85 MHz, which can process the five-level DWT analysis of a 128 x 128 x 128 fMRI volume image in 20 ms.

Low-power systolic array processor architecture for FSBM video motion estimation

A novel power-efficient systolic array architecture is proposed for full search block matching (FSBM) motion estimation, where the partial distortion elimination algorithm is used to dynamically switch off the computation of eliminated partial candidate blocks. The RTL-level simulation shows that the proposed architecture can reduce the power consumption of the computation part of the algorithm to about 60% of that of the conventional 2D systolic arrays.

Reconfigurable video Motion Estimation processor

In this paper, a new reconfigurable multi-standard Motion Estimation (ME) architecture is proposed and a standard-cell based design study is presented. The architecture exhibits simpler control, high throughput and relative low hardware cost and is highly competitive when compared with existing designs for specific video standards. ©2007 IEEE.

Approaches to crystallization from ionic liquids: complex solvents-complex results, or, a strategy for controlled formation of new supramolecular architectures?

There are now more than 1200 papers a year describing research results using the 'neoteric' solvents, known as ionic liquids (ILs). If ILs are such highly studied solvents, why has there been so comparatively little research in their use in crystallization? Here we explore this question and discuss possible strategies for utilization of the mundane and the unique aspects of ILs for novel crystallization strategies including crystallization of high and low melting solids using thermal shifts; ''solvothermal'' techniques; slow diffusion; electrocrystallization; and use of a co-solvent. The results presented here and those appearing in the literature indicate both the complex nature of these solvents and their promise in delivering unique solvation, metal ion coordination numbers, coordination polymer motifs, and metal-anion interactions, to name but a few. These complex, but fascinating, results and the promise of much more intimate control over crystallization processes will drive a growing interest in using ILs as crystallization solvents.

Online CORDIC algorithm and VLSI architecture for implementing QR-array processors

A novel most significant digit first CORDIC architecture is presented that is suitable for the VLSI design of systolic array processor cells for performing QR decomposition. This is based on an on-line CORDIC algorithm with a constant scale factor and a latency independent of the wordlength. This has been derived through the extension of previously published CORDIC algorithms. It is shown that simplifying the calculation of convergence bounds also greatly simplifies the derivation of suitable VLSI architectures. Design studies, based on a 0.35-µ CMOS standard cell process, indicate that 20 such QR processor cells operating at rates suitable for radar beamfoming can be readily accommodated on a single chip.