45 resultados para adaptive backstepping droop controller design
Resumo:
This paper presents the design of a single chip adaptive beamformer which contains 5 million transistors and can perform 50 GigaFlops. The core processor of the adaptive beamformer is a QR-array processor implemented on a fully efficient linear systolic architecture. The paper highlights a number of rapid design techniques that have been used to realize the design. These include an architecture synthesis tool for quickly developing the circuit architecture and the utilization of a library of parameterizable silicon intellectual property (IP) cores, to rapidly develop the circuit layouts.
Resumo:
In this paper, we propose a system level design approach considering voltage over-scaling (VOS) that achieves error resiliency using unequal error protection of different computation elements, while incurring minor quality degradation. Depending on user specifications and severity of process variations/channel noise, the degree of VOS in each block of the system is adaptively tuned to ensure minimum system power while providing "just-the-right" amount of quality and robustness. This is achieved, by taking into consideration block level interactions and ensuring that under any change of operating conditions, only the "less-crucial" computations, that contribute less to block/system output quality, are affected. The proposed approach applies unequal error protection to various blocks of a system-logic and memory-and spans multiple layers of design hierarchy-algorithm, architecture and circuit. The design methodology when applied to a multimedia subsystem shows large power benefits ( up to 69% improvement in power consumption) at reasonable image quality while tolerating errors introduced due to VOS, process variations, and channel noise.
Resumo:
A generic architecture for implementing a QR array processor in silicon is presented. This improves on previous research by considerably simplifying the derivation of timing schedules for a QR system implemented as a folded linear array, where account has to be taken of processor cell latency and timing at the detailed circuit level. The architecture and scheduling derived have been used to create a generator for the rapid design of System-on-a-Chip (SoC) cores for QR decomposition. This is demonstrated through the design of a single-chip architecture for implementing an adaptive beamformer for radar applications. Published as IEEE Trans Circuits and Systems Part II, Analog and Digital Signal Processing, April 2003 NOT Express Briefs. Parts 1 and II of Journal reorganised since then into Regular Papers and Express briefs
Resumo:
Maintaining the ecosystem is one of the main concerns in this modern age. With the fear of ever-increasing global warming, the UK is one of the key players to participate actively in taking measures to slow down at least its phenomenal rate. As an ingredient to this process, the Springer vehicle was designed and developed for environmental monitoring and pollutant tracking. This special issue paper highlighted the Springer hardware and software architecture including various navigational sensors, a speed controller, and an environmental monitoring unit. In addition, details regarding the modelling of the vessel were outlined based mainly on experimental data. The formulation of a fault tolerant multi-sensor data fusion technique was also presented. Moreover, control strategy based on a linear quadratic Gaussian controller was developed and simulated on the Springer model.
Gaussian controller is developed and simulated on the Springer model.
Resumo:
Local Controller Networks (LCNs) provide nonlinear control by interpolating between a set of locally valid, subcontrollers covering the operating range of the plant. Constructing such networks typically requires knowledge of valid local models. This paper describes a new genetic learning approach to the construction of LCNs directly from the dynamic equations of the plant, or from modelling data. The advantage is that a priori knowledge about valid local models is not needed. In addition to allowing simultaneous optimisation of both the controller and validation function parameters, the approach aids transparency by ensuring that each local controller acts independently of the rest at its operating point. It thus is valuable for simultaneous design of the LCNs and identification of the operating regimes of an unknown plant. Application results from a highly nonlinear pH neutralisation process and its associated neural network representation are utilised to illustrate these issues.
Resumo:
In this paper, we present a random iterative graph based hyper-heuristic to produce a collection of heuristic sequences to construct solutions of different quality. These heuristic sequences can be seen as dynamic hybridisations of different graph colouring heuristics that construct solutions step by step. Based on these sequences, we statistically analyse the way in which graph colouring heuristics are automatically hybridised. This, to our knowledge, represents a new direction in hyper-heuristic research. It is observed that spending the search effort on hybridising Largest Weighted Degree with Saturation Degree at the early stage of solution construction tends to generate high quality solutions. Based on these observations, an iterative hybrid approach is developed to adaptively hybridise these two graph colouring heuristics at different stages of solution construction. The overall aim here is to automate the heuristic design process, which draws upon an emerging research theme on developing computer methods to design and adapt heuristics automatically. Experimental results on benchmark exam timetabling and graph colouring problems demonstrate the effectiveness and generality of this adaptive hybrid approach compared with previous methods on automatically generating and adapting heuristics. Indeed, we also show that the approach is competitive with the state of the art human produced methods.