A scalable packet sorting circuit for high-speed WFQ packet scheduling

A novel implementation of a tag sorting circuit for a weighted fair queueing (WFQ) enabled Internet Protocol (IP) packet scheduler is presented. The design consists of a search tree, matching circuitry, and a custom memory layout. It is implemented using 130-nm silicon technology and supports quality of service (QoS) on networks at line speeds of 40 Gb/s, enabling next generation IP services to be deployed.

Fully hardware based WFQ architecture for high-speed QoS packet scheduling

A full hardware implementation of a Weighted Fair Queuing (WFQ) packet scheduler is proposed. The circuit architecture presented has been implemented using Altera Stratix II FPGA technology, utilizing RLDII and QDRII memory components. The circuit can provide fine granularity Quality of Service (QoS) support at a line throughput rate of 12.8Gb/s in its current implementation. The authors suggest that, due to the flexible and scalable modular circuit design approach used, the current circuit architecture can be targeted for a full ASIC implementation to deliver 50 Gb/s throughput. The circuit itself comprises three main components; a WFQ algorithm computation circuit, a tag/time-stamp sort and retrieval circuit, and a high throughput shared buffer. The circuit targets the support of emerging wireline and wireless network nodes that focus on Service Level Agreements (SLA's) and Quality of Experience.

Androgen deprivation results in time-dependent hypoxia in LNCaP prostate tumours; informed scheduling of the bioreductive drug AQ4N improves treatment response

Androgen withdrawal induces hypoxia in androgen-sensitive tissue; this is important as in the tumour microenvironment hypoxia is known to drive malignant progression. This study examined the time-dependent effect of androgen deprivation therapy (ADT) on tumour oxygenation and investigated the role of ADT-induced hypoxia on malignant progression in prostate tumours. LNCaP xenografted tumours were treated with anti-androgens and tumour oxygenation measured. Dorsal skin fold chambers (DSF) were used to image tumour vasculature in vivo. Quantitative PCR (QPCR) identified differential gene expression following treatment with bicalutamide. Bicalutamide and vehicle-only treated tumours were re-established in vitro and invasion and sensitivity to docetaxel were measured. Tumour growth delay was calculated following treatment with bicalutamide combined with the bioreductive drug AQ4N. Tumour oxygenation measurements showed a precipitate decrease following initiation of ADT. A clinically relevant dose of bicalutamide (2mg/kg/day) decreased tumour oxygenation by 45% within 24h, reaching a nadir of 0.09% oxygen (0.67±0.06 mmHg) by day 7; this persisted until day 14 when it increased up to day 28. Using DSF chambers, LNCaP tumours treated with bicalutamide showed loss of small vessels at days 7 and 14 with revascularization occurring by day 21. QPCR showed changes in gene expression consistent with the vascular changes and malignant progression. Cells from bicalutamide-treated tumours were more malignant than vehicle-treated controls. Combining bicalutamide with AQ4N (50mg/kg; single dose) caused greater tumour growth delay than bicalutamide alone. This study shows that bicalutamide-induced hypoxia selects for cells that show malignant progression; targeting hypoxic cells may provide greater clinical benefit.

A Kernel Interleaved Scheduling Method for Streaming Applications on Soft-core Vector Processors

Massively parallel networks of highly efficient, high performance Single Instruction Multiple Data (SIMD) processors have been shown to enable FPGA-based implementation of real-time signal processing applications with performance and
cost comparable to dedicated hardware architectures. This is achieved by exploiting simple datapath units with deep processing pipelines. However, these architectures are highly susceptible to pipeline bubbles resulting from data and control hazards; the only way to mitigate against these is manual interleaving of
application tasks on each datapath, since no suitable automated interleaving approach exists. In this paper we describe a new automated integrated mapping/scheduling approach to map algorithm tasks to processors and a new low-complexity list scheduling technique to generate the interleaved schedules. When applied to a spatial Fixed-Complexity Sphere Decoding (FSD) detector
for next-generation Multiple-Input Multiple-Output (MIMO) systems, the resulting schedules achieve real-time performance for IEEE 802.11n systems on a network of 16-way SIMD processors on FPGA, enable better performance/complexity balance than current approaches and produce results comparable to handcrafted implementations.

Generic scheduling methods for a linear QR array SoC processor

A scheduling method for implementing a generic linear QR array processor architecture is presented. This improves on previous work. It also considerably simplifies the derivation of schedules for a folded linear system, where detailed account has to be taken of processor cell latency. The architecture and scheduling derived provide the basis of a generator for the rapid design of System-on-a-Chip (SoC) cores for QR decomposition.