3D Simulations of Surface Harmonic Generation with few-cycle laser pulses

The mechanism of harmonic generation in the interaction of short laser pulses with solid targets holds the promise for the production of intense attosecond pulses. Using the three dimensional code ILLUMINATION we have performed simulations pertaining to an experimentally realizable parameter range by high power laser systems to become available in the near future. The emphasis of the investigation is on the coherent nature of the emission. We studied the influence of the plasma scale length on the harmonic efficiency, angular distribution and the focusability using a post processing scheme in which the far-field of the emission is calculated. It is found that the presence of an extended density profile reduces significantly the transverse coherence length of the emitted XUV light. The different stages of the interaction for two particular cases can be followed with the help of movies.

Area-efficient high-speed 3D DWT processor architecture

An area-efficient high-throughput architecture based on distributed arithmetic is proposed for 3D discrete wavelet transform (DWT). The 3D DWT processor was designed in VHDL and mapped to a Xilinx Virtex-E FPGA. The processor runs up to 85 MHz, which can process the five-level DWT analysis of a 128 x 128 x 128 fMRI volume image in 20 ms.

High-performance 3D median filter architecture for medical image despeckling

A high-sample rate 3D median filtering processor architecture is proposed, based on a novel 3D median filtering algorithm, that can reduce the computing complexity in comparison with the traditional bubble sorting algorithm. A 3 x 3 x 3 filter processor is implemented in VHDL, and the simulation verifies that the processor can process a 128 x 128 x 96 MRI image in 0.03 seconds while running at 50 MHz.

Optimisation of trench isolated bipolar transistors on SOI substrates by 3D electro-thermal simulations

This paper provides a comprehensive analysis of thermal resistance of trench isolated bipolar transistors on SOI substrates based on 3D electro-thermal simulations calibrated to experimental data. The impact of emitter length, width, spacing and number of emitter fingers on thermal resistance is analysed in detail. The results are used to design and optimise transistors with minimum thermal resistance and minimum transistor area. (c) 2007 Elsevier Ltd. All rights reserved.