Design of latch-based C-element

The C-element logic gate is a key component for constructing asynchronous control in silicon integrated circuits. The purpose of this reported work is to introduce a new speed-independent C-element design, which is synthesised by the asynchronous Petrify design tool to ensure it is composed of sequential digital latches rather than complex gates. The benefits are that it guarantees correct speed-independent operation, together with easy integration in modern design flows and processes. It is compared to an equivalent speed-independent complex gate C-element design generated by Petrify in a 130 nm semiconductor process.

Design and analysis of dual-rail circuits for security applications

Dual-rail encoding, return-to-spacer protocol, and hazard-free logic can be used to resist power analysis attacks by making energy consumed per clock cycle independent of processed data. Standard dual-rail logic uses a protocol with a single spacer, e.g., all-zeros, which gives rise to energy balancing problems. We address these problems by incorporating two spacers; the spacers alternate between adjacent clock cycles. This guarantees that all gates switch in every clock cycle regardless of the transmitted data values. To generate these dual-rail circuits, an automated tool has been developed. It is capable of converting synchronous netlists into dual-rail circuits and it is interfaced to industry CAD tools. Dual-rail and single-rail benchmarks based upon the advanced encryption standard (AES) have been simulated and compared in order to evaluate the method and the tool.

Containing the Nanometer "Pandora-Box": Cross-Layer Design Techniques for Variation Aware Low Power Systems

The demand for richer multimedia services, multifunctional portable devices and high data rates can only been visioned due to the improvement in semiconductor technology. Unfortunately, sub-90 nm process nodes uncover the nanometer Pandora-box exposing the barriers of technology scaling-parameter variations, that threaten the correct operation of circuits, and increased energy consumption, that limits the operational lifetime of today's systems. The contradictory design requirements for low-power and system robustness, is one of the most challenging design problems of today. The design efforts are further complicated due to the heterogeneous types of designs ( logic, memory, mixed-signal) that are included in today's complex systems and are characterized by different design requirements. This paper presents an overview of techniques at various levels of design abstraction that lead to low power and variation aware logic, memory and mixed-signal circuits and can potentially assist in meeting the strict power budgets and yield/quality requirements of future systems.

Rapid design of discrete orthonormal wavelet transforms using silicon IP components

A rapid design methodology for orthonormal wavelet transform cores has been developed. This methodology is based on a generic, scaleable architecture utilising time-interleaved coefficients for the wavelet transform filters. The architecture has been captured in VHDL and parameterised in terms of wavelet family, wavelet type, data word length and coefficient word length. The control circuit is embedded within the cores and allows them to be cascaded without any interface glue logic for any desired level of decomposition. Case studies for stand alone and cascaded silicon cores for single and multi-stage wavelet analysis respectively are reported. The design time to produce silicon layout of a wavelet based system has been reduced to typically less than a day. The cores are comparable in area and performance to handcrafted designs. The designs are portable across a range of foundries and are also applicable to FPGA and PLD implementations.

A Coordination and Ligand Replacement Based Three-Input Colorimetric Logic Gate Sensing Platform for Melamine, Mercury Ions, and Cysteine

Discrimination of different species in various target scopes within a single sensing platform can provide many advantages such as simplicity, rapidness, and cost effectiveness. Here we design a three-input colorimetric logic gate based on the aggregation and anti-aggregation of gold nanoparticles (Au NPs) for the sensing of melamine, cysteine, and Hg2+. The concept takes advantages of the highly specific coordination and ligand replacement reactions between melamine, cysteine, Hg2+, and Au NPs. Different outputs are obtained with the combinational inputs in the logic gates, which can serve as a reference to discriminate different analytes within a single sensing platform. Furthermore, besides the intrinsic sensitivity and selectivity of Au NPs to melamine-like compounds, the “INH” gates of melamine/cysteine and melamine/Hg2+ in this logic system can be employed for sensitive and selective detections of cysteine and Hg2+, respectively.

Energy versus data integrity trade-offs in embedded high-density logic compatible dynamic memories

Current variation aware design methodologies, tuned for worst-case scenarios, are becoming increasingly pessimistic from the perspective of power and performance. A good example of such pessimism is setting the refresh rate of DRAMs according to the worst-case access statistics, thereby resulting in very frequent refresh cycles, which are responsible for the majority of the standby power consumption of these memories. However, such a high refresh rate may not be required, either due to extremely low probability of the actual occurrence of such a worst-case, or due to the inherent error resilient nature of many applications that can tolerate a certain number of potential failures. In this paper, we exploit and quantify the possibilities that exist in dynamic memory design by shifting to the so-called approximate computing paradigm in order to save power and enhance yield at no cost. The statistical characteristics of the retention time in dynamic memories were revealed by studying a fabricated 2kb CMOS compatible embedded DRAM (eDRAM) memory array based on gain-cells. Measurements show that up to 73% of the retention power can be saved by altering the refresh time and setting it such that a small number of failures is allowed. We show that these savings can be further increased by utilizing known circuit techniques, such as body biasing, which can help, not only in extending, but also in preferably shaping the retention time distribution. Our approach is one of the first attempts to access the data integrity and energy tradeoffs achieved in eDRAMs for utilizing them in error resilient applications and can prove helpful in the anticipated shift to approximate computing.

A Design & Feasibility Study of the Spaced Learning Programme

Objectives There is evidence from neuroscience, cognitive psychology and educational research that the delivery of a stimulus in a spaced format (over time) rather than a massed format (all at once) leads to more effective learning. This project aimed to pilot spaced learning materials using various spacing lengths for GCSE science by exploring the feasibility of introducing spaced leaning into regular classrooms and by evaluating teacher fidelity to the materials. The spaced learning methods will then be compared with traditional science revision techniques and a programme manual will be produced. Design A feasibility study. Methods A pilot study (4 schools) was carried out to examine the feasibility and teacher fidelity to the materials, using pupil workshops and teacher interviews. A subsequent random assignment experimental study (12 schools) will involve pre and post testing of students on a science attainment measure and a post-test implementation questionnaire. Results The literature review found that longer spacing intervals between repetitions of material (>24 hours) may be optimal for long term memory formation than shorter intervals. A logic model was developed to inform the design of various programme variants for the pilot and experimental study. This paper will report qualitative data from the initial pilot study. Conclusions The paper uses this research project as an example to explain the importance of conducting pilot work and small scale experimental studies to explore the feasibility and inform the design of educational interventions, rather than prematurely moving to RCT type studies.