Performance assessment of nanoscale double- and triple- gate FinFETs

This is the first paper to describe performance assessment of triple and double gate FinFETs for High Performance (HP), Low Operating Power (LOP) and Low Standby Power (LSTP) logic technologies is investigated. The impact of gate work-function, spacer width, lateral source/drain doping gradient, fin aspect ratio, fin thickness on device performance, has been analysed in detail and guidelines are presented to meet ITRS specification at 65 and 45 nm nodes. Optimal design of lateral source/drain doping profile can not only effectively control short channel effects, yielding low off-current, but also achieve low values of intrinsic gate delay.

Power dissipation in nanoscale conductors: classical, semi-classical and quantum dynamics

Modelling Joule heating is a difficult problem because of the need to introduce correct correlations between the motions of the ions and the electrons. In this paper we analyse three different models of current induced heating (a purely classical model, a fully quantum model and a hybrid model in which the electrons are treated quantum mechanically and the atoms are treated classically). We find that all three models allow for both heating and cooling processes in the presence of a current, and furthermore the purely classical and purely quantum models show remarkable agreement in the limit of high biases. However, the hybrid model in the Ehrenfest approximation tends to suppress heating. Analysis of the equations of motion reveals that this is a consequence of two things: the electrons are being treated as a continuous fluid and the atoms cannot undergo quantum fluctuations. A means for correcting this is suggested.

6-T SRAM cell design with nanoscale double-gate SOI MOSFETs: impact of source/drain engineering and circuit topology

The impact of source/drain engineering on the performance of a six-transistor (6-T) static random access memory (SRAM) cell, based on 22 nm double-gate (DG) SOI MOSFETs, has been analyzed using mixed-mode simulation, for three different circuit topologies for low voltage operation. The trade-offs associated with the various conflicting requirements relating to read/write/standby operations have been evaluated comprehensively in terms of eight performance metrics, namely retention noise margin, static noise margin, static voltage/current noise margin, write-ability current, write trip voltage/current and leakage current. Optimal design parameters with gate-underlap architecture have been identified to enhance the overall SRAM performance, and the influence of parasitic source/drain resistance and supply voltage scaling has been investigated. A gate-underlap device designed with a spacer-to-straggle (s/sigma) ratio in the range 2-3 yields improved SRAM performance metrics, regardless of circuit topology. An optimal two word-line double-gate SOI 6-T SRAM cell design exhibits a high SNM similar to 162 mV, I-wr similar to 35 mu A and low I-leak similar to 70 pA at V-DD = 0.6 V, while maintaining SNM similar to 30% V-DD over the supply voltage (V-DD) range of 0.4-0.9 V.

Engineering source/drain extension regions in nanoscale double gate (DG) SOI MOSFETs: Analytical model and design considerations

In this paper, we propose for the first time, an analytical model for short channel effects in nanoscale source/drain extension region engineered double gate (DG) SOI MOSFETs. The impact of (i) lateral source/drain doping gradient (d), (ii) spacer width (s), (iii) spacer to doping gradient ratio (s/d) and (iv) silicon film thickness (T-si), on short channel effects - threshold voltage (V-th) and subthreshold slope (S), on-current (I-on), off-current (I-on) and I-on/I-off is extensively analysed by using the analytical model and 2D device simulations. The results of the analytical model confirm well with simulated data over the entire range of spacer widths, doping gradients and effective channel lengths. Results show that lateral source/drain doping gradient along with spacer width can not only effectively control short channel effects, thus presenting low off-current, but can also be optimised to achieve high values of on-currents. The present work provides valuable design insights in the performance of nanoscale DG Sol devices with optimal source/drain engineering and serves as a tool to optimise important device and technological parameters for 65 nm technology node and below. (c) 2006 Elsevier Ltd. All rights reserved.

Influence of test methodology and probe geometry on nanoscale fatigue mechanisms of diamond-like carbon thin film

The aim of this paper is to investigate the mechanism of nanoscale fatigue using nano-impact and multiple-loading cycle nanoindentation tests, and compare it to previously reported findings of nanoscale fatigue using integrated stiffness and depth sensing approach. Two different film loading mechanism, loading history and indenter shapes are compared to comprehend the influence of test methodology on the nanoscale fatigue failure mechanisms of DLC film. An amorphous 100 nm thick DLC film was deposited on a 500 μm silicon substrate using sputtering of graphite target in pure argon atmosphere. Nano-impact and multiple-load cycle indentations were performed in the load range of 100 μN to 1000 μN and 0.1 mN to 100 mN, respectively. Both test types were conducted using conical and Berkovich indenters. Results indicate that for the case of conical indenter, the combination of nano-impact and multiple-loading cycle nanoindentation tests provide information on the life and failure mechanism of DLC film, which is comparable to the previously reported findings using the integrated stiffness and depth sensing approach. However, the comparison of results is sensitive to the applied load, loading mechanism, test-type and probe geometry. The loading mechanism and load history is therefore critical which also leads to two different definitions of film failure. The choice of exact test methodology, load and probe geometry should therefore be dictated by the in-service tribological conditions, and where necessary both test methodologies can be used to provide better insights of failure mechanism. Molecular dynamics (MD) simulations of the elastic response of nanoindentation is reported, which indicates that the elastic modulus of the film measured using MD simulation was higher than that experimentally measured. This difference is attributed to the factors related to the presence of material defects, crystal structure, residual stress, indenter geometry and loading/unloading rate differences between the MD and experimental results.

Transport in nanoscale systems: the microcanonical versus grand-canonical picture

We analyse a picture of transport in which two large but finite charged electrodes discharge across a nanoscale junction. We identify a functional whose minimization, within the space of all bound many-body wavefunctions, defines an instantaneous steady state. We also discuss factors that favour the onset of steady-state conduction in such systems, make a connection with the notion of entropy, and suggest a novel source of steady-state noise. Finally, we prove that the true many-body total current in this closed system is given exactly by the one-electron total current, obtained from time-dependent density-functional theory.

Power dissipation in nanoscale conductors

A previous tight-binding model of power dissipation in a nanoscale conductor under an applied bias is extended to take account of the local atomic topology and the local electronic structure. The method is used to calculate the power dissipated at every atom in model nanoconductor geometries: a nanoscale constriction, a one-dimensional atomic chain between two electrodes with a resonant double barrier, and an irregular nanowire with sharp corners. The local power is compared with the local current density and the local density of states. A simple relation is found between the local power and the current density in quasiballistic geometries. A large enhancement in the power at special atoms is found in cases of resonant and anti-resonant transmission. Such systems may be expected to be particularly unstable against current-induced modifications.

Comparative analysis of nanoscale MOS device architectures for RF applications

This paper provides valuable design insights for optimizing device parameters for nanoscale planar and vertical SOI MOSFETs. The suitability of nanoscale non-planar FinFETs and classical planar single and double gate SOI MOSFETs for rf applications is examined via extensive 3D device simulations and detailed interpretation. The origin of higher parasitic capacitance in FinFETs, compared to planar MOSFETs is examined. RF figures of merit for planar and vertical MOS devices are compared, based on layout-area calculations.

Nanoscale ferroelectrics machined from single crystals

This paper summarises some of the most recent work that has been done on nanoscale ferroelectrics as a result of a joint collaborative research effort involving groups in Queen's University Belfast, the University of Cambridge and the University of St. Andrews. Attempts have been made to observe fundamental effects of reduced size, and increasing morphological complexity, on ferroelectric behaviour by studying the functional response and domain characteristics in nanoscale single crystal material, whose size and morphology have been defined by Focused Ion Beam (FIB) patterning. This approach to nanoshape fabrication has allowed the following broad statements to be made: (i) in single crystal BaTiO3 sheets, permittivity and phase transition behaviour is not altered from that of bulk material down to a thickness of similar to 75 nm; (ii) in single crystal BaTiO3 sheets and nanowires changes in observed domain morphologies are consistent with large scale continuum modeling.

Performance projections and design optimization of planar double gate SOI MOSFETs for logic technology applications

In this paper, by investigating the influence of source/drain extension region engineering (also known as gate-source/drain underlap) in nanoscale planar double gate (DG) SOI MOSFETs, we offer new insights into the design of future nanoscale gate-underlap DG devices to achieve ITRS projections for high performance (HP), low standby power (LSTP) and low operating power (LOP) logic technologies. The impact of high-kappa gate dielectric, silicon film thickness, together with parameters associated with the lateral source/drain doping profile, is investigated in detail. The results show that spacer width along with lateral straggle can not only effectively control short-channel effects, thus presenting low off-current in a gate underlap device, but can also be optimized to achieve lower intrinsic delay and higher on-off current ratio (I-on/I-off). Based on the investigation of on-current (I-on), off-current (I-off), I-on/I-off, intrinsic delay (tau), energy delay product and static power dissipation, we present design guidelines to select key device parameters to achieve ITRS projections. Using nominal gate lengths for different technologies, as recommended from ITRS specification, optimally designed gate-underlap DG MOSFETs with a spacer-to-straggle (s/sigma) ratio of 2.3 for HP/LOP and 3.2 for LSTP logic technologies will meet ITRS projection. However, a relatively narrow range of lateral straggle lying between 7 to 8 nm is recommended. A sensitivity analysis of intrinsic delay, on-current and off-current to important parameters allows a comparative analysis of the various design options and shows that gate workfunction appears to be the most crucial parameter in the design of DG devices for all three technologies. The impact of back gate misalignment on I-on, I-off and tau is also investigated for optimized underlap devices.

Ferroelectrics at the Nanoscale

There are several factors which make the investigation and understanding of nanoscale ferroelectrics particularly timely and important. Firstly, there is a market pressure, primarily from the electronics industry, to integrate ferroelectrics into devices with progressive decreases in size and increases in morphological complexity. This is perhaps best illustrated through the roadmaps for product development in FeRAM (Ferroelectric Randorn Access Memory) where the need for increases in bit density will require a move from 2D planar capacitor structures to 3D trenched capacitors in the next few years. Secondly, there is opportunity for novel exploration, as it is only relatively recently that developments in thin film growth of complex oxides, self-assembly techniques and high-resolution 'top-down' patterning have converged to allow the fabrication of isolated and well-defined ferroelectric nanoshapes, the properties of which are not known. Thirdly, there is an expectation that the behaviour of small scale ferroelectrics will be different from bulk, as this group of functional materials is highly sensitive to boundary/surface conditions, which are expected to dominate the overall response when sizes are reduced into the nanoscale regime. This feature article attempts to introduce some of the current areas of discovery and debate surrounding studies on ferroelectrics at the nanoscale. The focus is directed primarily at the search for novel size-related properties and behaviour which are not necessarily observed in bulk.

Physics of electron beam ion traps and sources

This paper presents the basic physics underlying the operation of electron beam ion traps and sources, with the machine physics underlying their operation being described in some detail. Predictions arising from this description are compared with some diagnostic measurements.

Fabrication and characterisation of high resistivity SOI substrates for monolithic high energy physics detectors

Silicon on Insulator (SOI) substrates offer a promising platform for monolithic high energy physics detectors with integrated read-out electronics and pixel diodes. This paper describes the fabrication and characterisation of specially-configured SOI substrates using improved bonded wafer ion split and grind/polish technologies. The crucial interface between the high resistivity handle silicon and the SOI buried oxide has been characterised using both pixel diodes and circular geometry MOS transistors. Pixel diode breakdown voltages were typically greater than 100V and average leakage current densities at 70 V were only 55 nA/ sq cm. MOS transistors subjected to 24 GeV proton irradiation showed an increased SOI buried oxide trapped charge of only 3.45x1011cn-2 for a dose of 2.7Mrad