Generic Architecture and Semiconductor Intellectual Property Cores for Avanced Encryption Standard Cryptography

A generic architecture for implementing the advanced encryption standard (AES) encryption algorithm in silicon is proposed. This allows the instantiation of a wide range of chip specifications, with these taking the form of semiconductor intellectual property (IP) cores. Cores implemented from this architecture can perform both encryption and decryption and support four modes of operation: (i) electronic codebook mode; (ii) output feedback mode; (iii) cipher block chaining mode; and (iv) ciphertext feedback mode. Chip designs can also be generated to cover all three AES key lengths, namely 128 bits, 192 bits and 256 bits. On-the-fly generation of the round keys required during decryption is also possible. The general, flexible and multi-functional nature of the approach described contrasts with previous designs which, to date, have been focused on specific implementations. The presented ideas are demonstrated by implementation in FPGA technology. However, the architecture and IP cores derived from this are easily migratable to other silicon technologies including ASIC and PLD and are capable of covering a wide range of modem communication systems cryptographic requirements. Moreover, the designs produced have a gate count and throughput comparable with or better than the previous one-off solutions.

WEBCOM-G: A candidate middleware for Grid-Ireland

WebCom-G is a fledgling Grid Operating System, designed to provide independent service access through interoperability with existing middlewares. It offers an expressive programming model that automatically handles task synchronisation – load balancing, fault tolerance, and task allocation are handled at the WebCom-G system level – without burdening the application writer. These characteristics, together with the ability of its computing model to mix evaluation strategies to match the characteristics of the geographically dispersed facilities and the overall problem- solving environment, make WebCom-G a promising grid middleware candidate.

Virtex FPGA Implementation of a Pipelined Adaptive LMS Predictor for Electronic Support Measures Receivers

High-speed field-programmable gate array (FPGA) implementations of an adaptive least mean square (LMS) filter with application in an electronic support measures (ESM) digital receiver, are presented. They employ "fine-grained" pipelining, i.e., pipelining within the processor and result in an increased output latency when used in the LMS recursive system. Therefore, the major challenge is to maintain a low latency output whilst increasing the pipeline stage in the filter for higher speeds. Using the delayed LMS (DLMS) algorithm, fine-grained pipelined FPGA implementations using both the direct form (DF) and the transposed form (TF) are considered and compared. It is shown that the direct form LMS filter utilizes the FPGA resources more efficiently thereby allowing a 120 MHz sampling rate.

Incorporation of chitosan in acrylic bone cement: Effect on antibiotic release, bacterial biofilm formation and mechanical properties

Bacterial infection remains a significant problem following total joint replacement. Efforts to prevent recurrent implant infection, including the use of antibiotic-loaded bone cement for implant fixation at the time of revision surgery, are not always successful. In this in vitro study, we investigated whether the addition of chitosan to gentamicin-loaded Palacos® R bone cement increased antibiotic release and prevented bacterial adherence and biofilm formation by Staphylococcus spp. clinical isolates. Furthermore, mechanical tests were performed as a function of time post-polymerisation in pseudo-physiological conditions. The addition of chitosan to gentamicin-loaded Palacos® R bone cement significantly decreased gentamicin release and did not increase the efficacy of the bone cement at preventing bacterial colonisation and biofilm formation. Moreover, the mechanical performance of cement containing chitosan was significantly reduced after 28 days of saline degradation with the compressive and bending strengths not in compliance with the minimum requirements as stipulated by the ISO standard for PMMA bone cement. Therefore, incorporating chitosan into gentamicin-loaded Palacos® R bone cement for use in revision surgery has no clinical antimicrobial benefit and the detrimental effect on mechanical properties could adversely affect the longevity of the prosthetic joint.

Special issue on design and programming of signal processors for multimedia communication:Special issue on design and programming of signal processors for multimedia communication

The technical challenges in the design and programming of signal processors for multimedia communication are discussed. The development of terminal equipment to meet such demand presents a significant technical challenge, considering that it is highly desirable that the equipment be cost effective, power efficient, versatile, and extensible for future upgrades. The main challenges in the design and programming of signal processors for multimedia communication are, general-purpose signal processor design, application-specific signal processor design, operating systems and programming support and application programming. The size of FFT is programmable so that it can be used for various OFDM-based communication systems, such as digital audio broadcasting (DAB), digital video broadcasting-terrestrial (DVB-T) and digital video broadcasting-handheld (DVB-H). The clustered architecture design and distributed ping-pong register files in the PAC DSP raise new challenges of code generation.

A new Jacobian matrix for optimal learning of single-layer neural networks

This paper investigates the learning of a wide class of single-hidden-layer feedforward neural networks (SLFNs) with two sets of adjustable parameters, i.e., the nonlinear parameters in the hidden nodes and the linear output weights. The main objective is to both speed up the convergence of second-order learning algorithms such as Levenberg-Marquardt (LM), as well as to improve the network performance. This is achieved here by reducing the dimension of the solution space and by introducing a new Jacobian matrix. Unlike conventional supervised learning methods which optimize these two sets of parameters simultaneously, the linear output weights are first converted into dependent parameters, thereby removing the need for their explicit computation. Consequently, the neural network (NN) learning is performed over a solution space of reduced dimension. A new Jacobian matrix is then proposed for use with the popular second-order learning methods in order to achieve a more accurate approximation of the cost function. The efficacy of the proposed method is shown through an analysis of the computational complexity and by presenting simulation results from four different examples.

Source/drain extension region engineering in nanoscale double gate SOI MOSFETs: Novel design methodology for low-voltage analog applications

The present paper proposes for the first time, a novel design methodology based on the optimization of source/drain extension (SDE) regions to significantly improve the trade-off between intrinsic voltage gain (A(vo)) and cut-off frequency (f(T)) in nanoscale double gate (DG) devices. Our results show that an optimally designed 25 nm gate length SDE region engineered DG MOSFET operating at drain current of 10 mu A/mu m, exhibits up to 65% improvement in intrinsic voltage gain and 85% in cut-off frequency over devices designed with abrupt SIDE regions. The influence of spacer width, lateral source/drain doping gradient and symmetric as well as asymmetrically designed SDE regions on key analog figures of merit (FOM) such as transconductance (g(m)), transconductance-to-current ratio (g(m)/I-ds), Early voltage (V-EA), output conductance (g(ds)) and gate capacitances are examined in detail. The present work provides new opportunities for realizing future low-voltage/low-power analog circuits with nanoscale SDE engineered DG MOSFETs. (C) 2007 Elsevier B.V. All rights reserved.

Cryptic species diversity in a widespread bumble bee complex revealed using mitochondrial DNA RFLPs

Cryptic species diversity is thought to be common within the class Insecta, posing problems for basic ecological and population genetic studies and conservation management. Within the temperate bumble bee (Bombus spp.) fauna, members of the subgenus Bombus sensu stricto are amongst the most abundant and widespread. However, their species diversity is controversial due to the extreme difficulty or inability morphologically to identify the majority of individuals to species. Our character-based phylogenetic analyses of partial CO1 (700 bp) from 39 individuals spread across their sympatric European ranges provided unequivocal support for five taxa (3-22 diagnostic DNA base pair sites per species). Inclusion of 20 Irish specimens to the dataset revealed >= 2.3% sequence divergence between taxa and 200 m) whilst B. cryptarum was relatively more abundant at higher altitudes. Bombus magnus was rarely encountered at urban sites. Both B. lucorum and B. terrestris are nowadays reared commercially for pollination and transported globally. Our RFLP approach to identify native fauna can underpin ecological studies of these important cryptic species as well as the impact of commercial bumble bees on them.

Germanium on sapphire

This paper explores the potential of germanium on sapphire (GeOS) wafers as a universal substrate for System on a Chip (SOC), mm wave integrated circuits (MMICs) and optical imagers. Ge has a lattice constant close to that of GaAs enabling epitaxial growth. Ge, GaAs and sapphire have relatively close temperature coefficients of expansion (TCE), enabling them to be combined without stress problems. Sapphire is transparent over the range 0.17 to 5.5 µm and has a very low loss tangent (a) for frequencies up to 72 GHz. Ge bonding to sapphire substrates has been investigated with regard to micro-voids and electrical quality of the Ge back interface. The advantages of a sapphire substrate for integrated inductors, coplanar waveguides and crosstalk suppression are also highlighted. MOS transistors have been fabricated on GeOS substrates, produced by the Smart-cut process, to illustrate the compatibility of the substrate with device processing. © 2008 World Scientific Publishing Company.