Soft X-ray harmonic comb from relativistic electron spikes

We demonstrate a new high-order harmonic generation mechanism reaching the "water window" spectral region in experiments with multiterawatt femtosecond lasers irradiating gas jets. A few hundred harmonic orders are resolved, giving mu J/sr pulses. Harmonics are collectively emitted by an oscillating electron spike formed at the joint of the boundaries of a cavity and bow wave created by a relativistically self-focusing laser in underdense plasma. The spike sharpness and stability are explained by catastrophe theory. The mechanism is corroborated by particle-in-cell simulations.

Field-programmable true random number generator

True random number generation is crucial in hardware security applications. Proposed is a voltage-controlled true random number generator that is inherently field-programmable. This facilitates increased entropy as a randomness source because there is more than one configuration state which lends itself to more compact and low-power architectures. It is evaluated through electrical characterisation and statistically through industry-standard randomness tests. To the best of the author's knowledge, it is one of the most efficient designs to date with respect to hardware design metrics.

The machinist landscape:Land Art Generator Initiative (Competition)

THE MACHINIST LANDSCAPE: AN ENTROPIC GRID OF VARIANCE
‘By drawing a diagram, a ground plan of a house, a street plan to the location of a site, or a topographic map, one draws a “logical two dimensional picture”. A “logical picture” differs from a natural or realistic picture in that it rarely looks like the thing it stands for.’
A Provisional Theory of Non-Sites, Robert Smithson (1968)

Between design and ground there are variances, deviations and gaps. These exist as physical interstices between what is conceptualised and what is realised; and they reveal moments in the design process that resist the reconciliation of people and their environment (McHarg 1963). The Machinist Landscape interrogates the significance of these variances through the contrasting processes of coppice and photovoltaic energy. It builds on the potential of these gaps, and in doing so proposes that these spaces of variance can reveal the complexity of relationships between consumption and remediation, design and nature.
Fresh Kills Park, and in particular the draft master plan (2006), offers a framework to explore this artificial construct. Central to the Machinist Landscape is the analysis of the landfill gas collection system, planned on a notional 200ft grid. Variations are revealed between this diagrammatic grid measure and that which has been constructed on the site. These variances between the abstract and the real offer the Machinist Landscape a powerful space of enquiry. Are these gaps a result of unexpected conditions below ground, topographic nuances or natural phenomena? Does this space of difference, between what is planned and what is constructed, have the potential to redefine the dynamic processes and relations with the land?
The Machinist Landscape is structured through this space of variance with an ‘entropic grid’, the under-storey of which hosts a carefully managed system of short-rotation coppice (SRC). The coppice, a medieval practice related to energy, product, and space, operates on theoretical and programmatic levels. It is planted along a structure of linear bunds, stabilized through coppice pole retaining structures and enriched with nutrients from coppice produced bio-char. Above the coppice is built an upper-storey of photovoltaic (PV); its structures fabricated from the coppiced timber and the PV produced with graphene from coppice charcoal processes.

Discrete cosine transform generator for VLSI synthesis

A generator for the automated design of Discrete Cosine Transform (DCT) cores is presented. This can be used to rapidly create silicon circuits from a high level specification. These compare very favourably with existing designs. The DCT cores produced are scaleable in terms of point size as well as input/output and coefficient wordlengths. This provides a high degree of flexibility. An example, 8-point 1D DCT design, produced occupies less than 0.92 mm when implemented in a 0.35µ double level metal CMOS technology. This can be clocked at a rate of 100MHz.

Blown Jet Vortex Generator Control of a Separated Diffuser Flow

The application of blown jet vortex generators to control flow separation in a diffuser with an opening angle of 10° has been studied using the computational fluid dynamics (CFD) code Fluent 6™. Experimental data is available for the uncontrolled flow in the diffuser. The section of the duct upstream of the diffuser has a height H equal to 15 mm; its length and breadth are 101H and 41H respectively; the diffuser has an expansion ratio of 4.7:1. Fully developed flow is achieved upstream of the diffuser. Pipes of diameters equal to 1.5%, 2.5% and 5% of H were considered; pitch angle was constant at 45° and yaw angle was fixed at 60°; velocity ratio was varied from 1.7 to 8.0; both co-rotating and counter-rotating arrays were studied. The best results were obtained with a counter-rotating array of generators with a hole diameter of 5% of H and a velocity ratio of 3.7.

Large-Scale Wind Generator Cascaded Tripping

Large scale wind farms are subject to tripping, as a consequence of turbine failure, over-sensitive protection, turbines not equipped with low-voltage ride through (LVRT), and reactive power compensation device defects which can lead to voltage rises. This paper considers pertinent issues which render tripping based on a study of LVRT and wind farm protection, with methods to avoid large scale wind generator tripping proposed. The results of LVRT field tests in Jiuquan, China in December 2012 show that the proposed approaches are effective. The paper also presents work which proposes an early warning system to forecast the risk of wind power tripping.

Modelling and Control of a Variable-Speed Switched Reluctance Generator based Wind Turbine

This paper studies the system modelling and control aspects of switched reluctance generator (SRG) based variable speed wind turbines. A control system is implemented to provide proper operation of the SRG as well as power tracking capabilities for varying wind speeds. The control system for the grid side inverter that will allow the SRG to properly generate power to the system is also presented. Studies are presented of both the SRG and inverter control systems capabilities during a balanced three-phase fault. The paper will demonstrate that the SRG based wind turbine presents a feasible variable wind speed solution with good fault response capabilities.

Inter-Area Power Oscillation Frequency Mode with Wind Turbine Generator in Irish Power System using PMU Data

Two case studies are presented in this paper to demonstrate the impact of different power system operation conditions on the power oscillation frequency modes in the Irish power system. A simplified 2 area equivalent of the Irish power system has been used in this paper, where area 1 represents the Republic of Ireland power system and area 2 represents the Northern Ireland power system.

The potential power oscillation frequency modes on the interconnector during different operation conditions have been analysed in this paper. The main objective of this paper is to analyse the influence of different operation conditions involving wind turbine generator (WTG) penetration on power oscillation frequency modes using phasor measurement unit (PMU) data.

Fast Fourier transform (FFT) analysis was performed to identify the frequency oscillation mode while correlation coefficient analysis was used to determine the source of the frequency oscillation. The results show that WTG, particularly fixed speed induction generation (FSIG), gives significant contribution to inter-area power oscillation frequency modes during high WTG operation.

A unique and robust single slice FPGA identification generator

In this paper, a new field-programmable gate array (FPGA) identification generator circuit is introduced based on physically unclonable function (PUF) technology. The new identification generator is able to convert flip-flop delay path variations to unique n-bit digital identifiers (IDs), while requiring only a single slice per ID bit by using 1-bit ID cells formed as hard-macros. An exemplary 128-bit identification generator is implemented on ten Xilinx Spartan-6 FPGA devices. Experimental results show an uniqueness of 48.52%, and reliability of 92.41% over a 25°C to 70°C temperature range and 10% fluctuation in supply voltage

Ultra-Compact and Robust FPGA-Based PUF Identification Generator

Physically Unclonable Functions (PUFs), exploit inherent manufacturing variations and present a promising solution for hardware security. They can be used for key storage, authentication and ID generations. Low power cryptographic design is also very important for security applications. However, research to date on digital PUF designs, such as Arbiter PUFs and RO PUFs, is not very efficient. These PUF designs are difficult to implement on Field Programmable Gate Arrays (FPGAs) or consume many FPGA hardware resources. In previous work, a new and efficient PUF identification generator was presented for FPGA. The PUF identification generator is designed to fit in a single slice per response bit by using a 1-bit PUF identification generator cell formed as a hard-macro. In this work, we propose an ultra-compact PUF identification generator design. It is implemented on ten low-cost Xilinx Spartan-6 FPGA LX9 microboards. The resource utilization is only 2.23%, which, to the best of the authors' knowledge, is the most compact and robust FPGA-based PUF identification generator design reported to date. This PUF identification generator delivers a stable range of uniqueness of around 50% and good reliability between 85% and 100%.

Generic SoC QR Array Processor for Adaptive Beamforming

A generic architecture for implementing a QR array processor in silicon is presented. This improves on previous research by considerably simplifying the derivation of timing schedules for a QR system implemented as a folded linear array, where account has to be taken of processor cell latency and timing at the detailed circuit level. The architecture and scheduling derived have been used to create a generator for the rapid design of System-on-a-Chip (SoC) cores for QR decomposition. This is demonstrated through the design of a single-chip architecture for implementing an adaptive beamformer for radar applications. Published as IEEE Trans Circuits and Systems Part II, Analog and Digital Signal Processing, April 2003 NOT Express Briefs. Parts 1 and II of Journal reorganised since then into Regular Papers and Express briefs