260 resultados para Programmable array logic


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Several logic gates and switches can be accessed from two different combinations of a single set of fluorophore, receptor and spacer components.

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A new strategy for remote reconfiguration of an antenna array far field radiation pattern is described. The scheme uses a pilot tone co-transmitted with a carrier signal from a location distant from that of a receive antenna array whose far field pattern is to be reconfigured. By mixing the co-transmitted signals locally at each antenna element in the array an IF signal is formed which defines an equivalent array spacing that can be made variable by tuning the frequency of the pilot tone with respect to the RF carrier. This makes the antenna array factor hence far field spatial characteristic reconfigurable on receive. For a 10 x 1 microstrip patch element array we show that the receive pattern can be made to vary from 35 to 10 degrees half power beam width as the difference frequency between the pilot and the carrier at 2.45 GHz varies between 10 MHz and 500 MHz carrier.

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Structural and functional information encoded in DNA combined with unique properties of nanomaterials could be of use for the construction of novel biocomputational circuits and intelligent biomedical nanodevices. However, at present their practical applications are still limited by either low reproducibility of fabrication, modest sensitivity, or complicated handling procedures. Here, we demonstrate the construction of label-free and switchable molecular logic gates that use specific conformation modulation of a guanine- and thymine- rich DNA, while the optical readout is enabled by the tunable alphabetical metamaterials, which serve as a substrate for surface enhanced Raman spectroscopy (MetaSERS). By computational and experimental investigations, we present a comprehensive solution to tailor the plasmonic responses of MetaSERS with respect to the metamaterial geometry, excitation energy, and polarization. Our tunable MetaSERS-based DNA logic is simple to operate, highly reproducible, and can be stimulated by ultra-low concentration of the external inputs, enabling an extremely sensitive detection of mercury ions.

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Currently there is extensive theoretical work on inconsistencies in logic-based systems. Recently, algorithms for identifying inconsistent clauses in a single conjunctive formula have demonstrated that practical application of this work is possible. However, these algorithms have not been extended for full knowledge base systems and have not been applied to real-world knowledge. To address these issues, we propose a new algorithm for finding the inconsistencies in a knowledge base using existing algorithms for finding inconsistent clauses in a formula. An implementation of this algorithm is then presented as an automated tool for finding inconsistencies in a knowledge base and measuring the inconsistency of formulae. Finally, we look at a case study of a network security rule set for exploit detection (QRadar) and suggest how these automated tools can be applied.

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To develop a detection method for human pathogenic Listeria monocytogenes, novel specific antibodies were obtained from hybridoma libraries generated by using formalin-killed and heat-killed L. monocytogenes as immunogens. Several monoclonal antibodies found to be specific to Listeria spp or L. monocytogenes were evaluated for their applicability as binders for bead array and sandwichELISA for detection of L. monocytogenes in buffer and in 11 different food types. The bead array format consistently demonstrated lower detection limits and was less affected by interference from food matrices than the sandwich ELISA format. However, the obtained detection limits were not sufficient to satisfy the required standard for L. monocytogenes testing. Therefore, the international organizationfor standardization (ISO 11290-1:1996) methods for pre-enrichment and enrichment were employed to increase the bacteria numbers. When compared to the standard plating method, the bead array was able to detect the bacteria with the same accuracy even at the 1 CFU level after only 24 hours of the enrichment period. In addition, Listeria-specific 3C3 and L. monocytogenes-specific 7G4 antibodies were successfully employed to construct a multiplex detection for Listeria, Salmonella and Campylobacter in a bead array format by combining with commercial Salmonella-specific and available Campylobacter-specific antibodies.

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The finite difference time domain (FDTD) method has direct applications in musical instrument modeling, simulation of environmental acoustics, room acoustics and sound reproduction paradigms, all of which benefit from auralization. However, rendering binaural impulse responses from simulated
data is not straightforward to accomplish as the calculated pressure at FDTD grid nodes does not contain any directional information. This paper addresses this issue by introducing a spherical array to capture sound pressure on a finite difference grid, and decomposing it into a plane-wave density
function. Binaural impulse responses are then constructed in the spherical harmonics domain by combining the decomposed grid data with free field head-related transfer functions. The effects of designing a spherical array in a Cartesian grid are studied, and emphasis is given to the relationships
between array sampling and the spatial and spectral design parameters of several finite-difference
schemes.

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Ambisonics and Higher Order Ambisonics (HOA) are scalable spatial audio techniques that attempt to present a sound scene to listeners over as large an area as possible. A localisation experiment was carried out to investigate the performance of a first and third order system at three listening positions - one in the centre and two off-centre - using a 5 m radius loudspeaker array. The results are briefly presented and compared to those of an earlier experiment on a 2.2 m loudspeaker array. In both experiments the off-centre listeners were placed such that the ratio of distance from the centre to the array radius was constant in both experiments. The test used a reverse target-pointer adjustment method to determine the error, both signed and absolute, for each combination of listening position and system. The results for both arrays were found to be very similar, suggesting that the relative amplitude of the loudspeakers, which were the same in both cases, was more dominant for localisation than the arrival time differences, which differed between array sizes.

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The paper presents IPPro which is a high performance, scalable soft-core processor targeted for image processing applications. It has been based on the Xilinx DSP48E1 architecture using the ZYNQ Field Programmable Gate Array and is a scalar 16-bit RISC processor that operates at 526MHz, giving 526MIPS of performance. Each IPPro core uses 1 DSP48, 1 Block RAM and 330 Kintex-7 slice-registers, thus making the processor as compact as possible whilst maintaining flexibility and programmability. A key aspect of the approach is in reducing the application design time and implementation effort by using multiple IPPro processors in a SIMD mode. For different applications, this allows us to exploit different levels of parallelism and mapping for the specified processing architecture with the supported instruction set. In this context, a Traffic Sign Recognition (TSR) algorithm has been prototyped on a Zedboard with the colour and morphology operations accelerated using multiple IPPros. Simulation and experimental results demonstrate that the processing platform is able to achieve a speedup of 15 to 33 times for colour filtering and morphology operations respectively, with a reduced design effort and time.

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In this paper, we propose a system level design approach considering voltage over-scaling (VOS) that achieves error resiliency using unequal error protection of different computation elements, while incurring minor quality degradation. Depending on user specifications and severity of process variations/channel noise, the degree of VOS in each block of the system is adaptively tuned to ensure minimum system power while providing "just-the-right" amount of quality and robustness. This is achieved, by taking into consideration block level interactions and ensuring that under any change of operating conditions, only the "less-crucial" computations, that contribute less to block/system output quality, are affected. The proposed approach applies unequal error protection to various blocks of a system-logic and memory-and spans multiple layers of design hierarchy-algorithm, architecture and circuit. The design methodology when applied to a multimedia subsystem shows large power benefits ( up to 69% improvement in power consumption) at reasonable image quality while tolerating errors introduced due to VOS, process variations, and channel noise.

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In this paper, we probed surface-enhanced Raman scattering (SERS) and surface-enhanced fluorescence (SEF) from probe molecule Rhodamine 6G (R6G) on self-standing Au nanorod array substrates made using a combination of anodization and potentiostatic electrodeposition. The initial substrates were embedded within a porous alumina template (AAO). By controlling the thickness of the AAO matrix, SEF and SERS were observed exhibiting an inverse relationship. SERS and SEF showed a non-linear response to the removal of AAO matrix due to an inhomogeneous plasmon activity across the nanorod which was supported by FDTD calculations. We showed that by optimizing the level of AAO thickness, we could obtain either maximized SERS, SEF or simultaneously observe both SERS and SEF together.

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The overall aim of the work presented in this paper has been to develop Montgomery modular multiplication architectures suitable for implementation on modern reconfigurable hardware. Accordingly, novel high-radix systolic array Montgomery multiplier designs are presented, as we believe that the inherent regular structure and absence of global interconnect associated with these, make them well-suited for implementation on modern FPGAs. Unlike previous approaches, each processing element (PE) comprises both an adder and a multiplier. The inclusion of a multiplier in the PE means that the need to pre-compute or store any multiples of the operands is avoided. This also allows very high-radix implementations to be realised, further reducing the amount of clock cycles per modular multiplication, while still maintaining a competitive critical delay. For demonstrative purposes, 512-bit and 1024-bit FPGA implementations using radices of 2(8) and 2(16) are presented. The subsequent throughput rates are the fastest reported to date.