'Whatever You Say, Say Nothing' : Researching Memory & Identity in Mid-Ulster, 1945-1969

The influence of collective memory on political identity in Ireland has been well documented. It has particular force in Northern Ireland where there is fundamental disagreement about how and why the conflict erupted and how it should be resolved. This article outlines some of the issues encountered by an ‘insider’ when attempting to record and analyse the conflicting memories of a range of Protestants and Catholics who grew up in Mid-Ulster in the decades preceding the Troubles. In particular, it considers the challenges and opportunities presented by a two-pronged approach to oral history: using testimony as evidence about historical experience in the past and as evidence about historical memory – both collective and individual – in the present.

Effect of Post-weld Heat-treatment on the Stress Corrosion Cracking Behaviour of Laser-welded Shape Memory NiTi Wires in Hanks’ Solution

In this study, the stress-corrosion cracking (SCC) behaviour of laser-welded NiTi wires before and after post-weld heat-treatment (PWHT) was investigated. The samples were subjected to slow strain rate testing (SSRT) under tensile loading in Hanks’ solution at 37.5 °C (or 310.5 K) at a constant anodic potential (200 mVSCE). The current density of the samples during the SSRT was captured by a potentiostat, and used as an indicator to determine the susceptibility to SCC. Fractography was analyzed using scanning-electron microscopy (SEM). The experimental results showed that the laser-welded sample after PWHT was immune to the SCC as evidenced by the stable current density throughout the SSRT. This is attributed to the precipitation of fine and coherent nano-sized Ni4Ti3 precipitates in the welded regions (weld zone, WZ and heat-affected zone, HAZ) after PWHT, resulting in (i) enrichment of TiO2 content in the passive film and (ii) higher resistance against the local plastic deformation in the welded regions.

Bandwidth selection by cross-validation for forecasting long memory financial time series

The paper addresses the issue of choice of bandwidth in the application of semiparametric estimation of the long memory parameter in a univariate time series process. The focus is on the properties of forecasts from the long memory model. A variety of cross-validation methods based on out of sample forecasting properties are proposed. These procedures are used for the choice of bandwidth and subsequent model selection. Simulation evidence is presented that demonstrates the advantage of the proposed new methodology.

On The Energy-Efficiency of Byte-Addressable Non-Volatile Memory

Non-Volatile Memory (NVM) technology holds promise to replace SRAM and DRAM at various levels of the memory hierarchy. The interest in NVM is motivated by the difficulty faced in scaling DRAM beyond 22 nm and, long-term, lower cost per bit. While offering higher density and negligible static power (leakage and refresh), NVM suffers increased latency and energy per memory access. This paper develops energy and performance models of memory systems and applies them to understand the energy-efficiency of replacing or complementing DRAM with NVM. Our analysis focusses on the application of NVM in main memory. We demonstrate that NVM such as STT-RAM and RRAM is energy-efficient for memory sizes commonly employed in servers and high-end workstations, but PCM is not. Furthermore, the model is well suited to quickly evaluate the impact of changes to the model parameters, which may be achieved through optimization of the memory architecture, and to determine the key parameters that impact system-level energy and performance.

The effects of TMS over dorsolateral prefrontal cortex on trans-saccadic memory of multiple objects

Humans typically make several rapid eye movements (saccades) per second. It is thought that visual working memory can retain and spatially integrate three to four objects or features across each saccade but little is known about this neural mechanism. Previously we showed that transcranial magnetic stimulation (TMS) to the posterior parietal cortex and frontal eye fields degrade trans-saccadic memory of multiple object features (Prime, Vesia, & Crawford, 2008, Journal of Neuroscience, 28(27), 6938-6949; Prime, Vesia, & Crawford, 2010, Cerebral Cortex, 20(4), 759-772.). Here, we used a similar protocol to investigate whether dorsolateral prefrontal cortex (DLPFC), an area involved in spatial working memory, is also involved in trans-saccadic memory. Subjects were required to report changes in stimulus orientation with (saccade task) or without (fixation task) an eye movement in the intervening memory interval. We applied single-pulse TMS to left and right DLPFC during the memory delay, timed at three intervals to arrive approximately 100ms before, 100ms after, or at saccade onset. In the fixation task, left DLPFC TMS produced inconsistent results, whereas right DLPFC TMS disrupted performance at all three intervals (significantly for presaccadic TMS). In contrast, in the saccade task, TMS consistently facilitated performance (significantly for left DLPFC/perisaccadic TMS and right DLPFC/postsaccadic TMS) suggesting a dis-inhibition of trans-saccadic processing. These results are consistent with a neural circuit of trans-saccadic memory that overlaps and interacts with, but is partially separate from the circuit for visual working memory during sustained fixation.

Logic and Memory Design Based on Unequal Error Protection for Voltage-scalable, Robust and Adaptive DSP Systems

In this paper, we propose a system level design approach considering voltage over-scaling (VOS) that achieves error resiliency using unequal error protection of different computation elements, while incurring minor quality degradation. Depending on user specifications and severity of process variations/channel noise, the degree of VOS in each block of the system is adaptively tuned to ensure minimum system power while providing "just-the-right" amount of quality and robustness. This is achieved, by taking into consideration block level interactions and ensuring that under any change of operating conditions, only the "less-crucial" computations, that contribute less to block/system output quality, are affected. The proposed approach applies unequal error protection to various blocks of a system-logic and memory-and spans multiple layers of design hierarchy-algorithm, architecture and circuit. The design methodology when applied to a multimedia subsystem shows large power benefits ( up to 69% improvement in power consumption) at reasonable image quality while tolerating errors introduced due to VOS, process variations, and channel noise.

Distributed Region-Based Memory Allocation and Synchronization

We present DRASync, a region-based allocator that implements a global address space abstraction for MPI programs with pointer-based data structures. The main features of DRASync are: (a) it amortizes communication among nodes to allow efficient parallel allocation in a global address space; (b) it takes advantage of bulk deallocation and good locality with pointer-based data structures; (c) it supports ownership semantics of regions by nodes akin to reader–writer locks, which makes for a high-level, intuitive synchronization tool in MPI programs, without sacrificing message-passing performance. We evaluate DRASync against a state-of-the-art distributed allocator and find that it produces comparable performance while offering a higher-level abstraction to programmers.

A Hardware Acceleration Scheme for Memory-Efficient Flow Processing

This paper presents a hardware solution for network flow processing at full line rate. Advanced memory architecture using DDR3 SDRAMs is proposed to cope with the flow match limitations in packet throughput, number of supported flows and number of packet header fields (or tuples) supported for flow identifications. The described architecture has been prototyped for accommodating 8 million flows, and tested on an FPGA platform achieving a minimum of 70 million lookups per second. This is sufficient to process internet traffic flows at 40 Gigabit Ethernet.

Competition between memory-keeping and memory-erasing decoherence channels

We study the competing effects of simultaneous Markovian and non-Markovian decoherence mechanisms acting on a single spin. We show the existence of a threshold in the relative strength of such mechanisms above which the spin dynamics becomes fully Markovian, as revealed by the use of several non-Markovianity measures. We identify a measure-dependent nested structure of such thresholds, hinting at a causality relationship among the various non-Markovianity witnesses used in our analysis. Our considerations are then used to argue the unavoidably non-Markovian evolution of a single-electron quantum dot exposed to both intrinsic and Markovian technical noise, the latter of arbitrary strength.