Small volume laboratory on a chip measurements incorporating the quartz crystal microbalance to measure the viscosity-density product of room temperature ionic liquids

A microfluidic glass chip system incorporating a quartz crystal microbalance (QCM) to measure the square root of the viscosity-density product of room temperature ionic liquids (RTILs) is presented. The QCM covers a central recess on a glass chip, with a seal formed by tightly clamping from above outside the sensing region. The change in resonant frequency of the QCM allows for the determination of the square root viscosity-density product of RTILs to a limit of similar to 10 kg m(-2) s(-0.5). This method has reduced the sample size needed for characterization from 1.5 ml to only 30 mu l and allows the measurement to be made in an enclosed system.

Thermal conductivity measurement of liquids in a microfluidic device

A new microfluidic-based approach to measuring liquid thermal conductivity is developed to address the requirement in many practical applications for measurements using small (microlitre) sample size and integration into a compact device. The approach also gives the possibility of high-throughput testing. A resistance heater and temperature sensor are incorporated into a glass microfluidic chip to allow transmission and detection of a planar thermal wave crossing a thin layer of the sample. The device is designed so that heat transfer is locally one-dimensional during a short initial time period. This allows the detected temperature transient to be separated into two distinct components: a short-time, purely one-dimensional part from which sample thermal conductivity can be determined and a remaining long-time part containing the effects of three-dimensionality and of the finite size of surrounding thermal reservoirs. Identification of the one-dimensional component yields a steady temperature difference from which sample thermal conductivity can be determined. Calibration is required to give correct representation of changing heater resistance, system layer thicknesses and solid material thermal conductivities with temperature. In this preliminary study, methanol/water mixtures are measured at atmospheric pressure over the temperature range 30-50A degrees C. The results show that the device has produced a measurement accuracy of within 2.5% over the range of thermal conductivity and temperature of the tests. A relation between measurement uncertainty and the geometric and thermal properties of the system is derived and this is used to identify ways that error could be further reduced.

Pre-storage of gelified reagents in a lab-on-a-foil system for rapid nucleic acid analysis

Reagent pre-storage in a microfluidic chip can enhance operator convenience, simplify the system design, reduce the cost of storage and shipment, and avoid the risk of cross-contamination. Although dry reagents have long been used in lateral flow immunoassays, they have rarely been used for nucleic acid-based point-of-care (POC) assays due to the lack of reliable techniques to dehydrate and store fragile molecules involved in the reaction. In this study, we describe a simple and efficient method for prolonged on-chip storage of PCR reagents. The method is based on gelification of all reagents required for PCR as a ready-to-use product. The approach was successfully implemented in a lab-on-a-foil system, and the gelification process was automated for mass production. Integration of reagents on-chip by gelification greatly facilitated the development of easy-to-use lab-on-a-chip (LOC) devices for fast and cost-effective POC analysis.

Exploring Virtual-Channel architecture in FPGA based Networks-on-Chip

A novel Networks-on-Chip (NoC) router architecture specified for FPGA based implementation with configurable Virtual-Channel (VC) is presented. Each pipeline stage of the proposed architecture has been optimized so that low packet propagation latency and reduced hardware overhead can be achieved. The proposed architecture enables high performance and cost effective VC NoC based on-chip system interconnects to be deployed on FPGA.

Reconfigurable system-on-a-chip motion estimation architecture for multi-standard video coding

A new domain-specific, reconfigurable system-on-a-chip (SoC) architecture is proposed for video motion estimation. This has been designed to cover most of the common block-based video coding standards, including MPEG-2, MPEG-4, H.264, WMV-9 and AVS. The architecture exhibits simple control, high throughput and relatively low hardware cost when compared with existing circuits. It can also easily handle flexible search ranges without any increase in silicon area and can be configured prior to the start of the motion estimation process for a specific standard. The computational rates achieved make the circuit suitable for high-end video processing applications, such as HDTV. Silicon design studies indicate that circuits based on this approach incur only a relatively small penalty in terms of power dissipation and silicon area when compared with implementations for specific standards. Indeed, the cost/performance achieved exceeds that of existing but specific solutions and greatly exceeds that of general purpose field programmable gate array (FPGA) designs.

JPEG encoder system-on-a-chip demonstrator

The design of a System-on-a-Chip (SoC) demonstrator for a baseline JPEG encoder core is presented. This combines a highly optimized Discrete Cosine Transform (DCT) and quantization unit with an entropy coder which has been realized using off-the-shelf synthesizable IP cores (Run-length coder, Huffman coder and data packer). When synthesized in a 0.35 µm CMOS process, the core can operate at speeds up to 100 MHz and contains 50 k gates plus 11.5 kbits of RAM. This is approximately 20% less than similar JPEG encoder designs reported in literature. When targeted at FPGA the core can operate up to 30 MHz and is capable of compressing 9-bit full-frame color input data at NTSC or PAL rates.

Wavelet packet transforms for system-on-chip applications

A methodology for the production of silicon cores for wavelet packet decomposition has been developed. The scheme utilizes efficient scalable architectures for both orthonormal and biorthogonal wavelet transforms. The cores produced from these architectures can be readily scaled for any wavelet function and are easily configurable for any subband structure. The cores are fully parameterized in terms of wavelet choice and appropriate wordlengths. Designs produced are portable across a range of silicon foundries as well as FPGA and PLD technologies. A number of exemplar implementations have been produced.

Linear QR architecture for a single chip adaptive beamformer

This paper presents the design of a novel single chip adaptive beamformer capable of performing 50 Gflops, (Giga-floating-point operations/second). The core processor is a QR array implemented on a fully efficient linear systolic architecture, derived using a mapping that allows individual processors for boundary and internal cell operations. In addition, the paper highlights a number of rapid design techniques that have been used to realise this system. These include an architecture synthesis tool for quickly developing the circuit architecture and the utilisation of a library of parameterisable silicon intellectual property (IP) cores, to rapidly develop detailed silicon designs.