Electrical Characterisation of SOI Substrates Incorporating WSix Ground Planes

Silicon-on-insulator (SOI) substrates incorporating tungsten silicide ground planes (GPs) have been shown to offer the lowest reported crosstalk figure of merit for application in mixed signal integrated circuits. The inclusion of the silicide layer in the structure may lead to stress or defects in the overlying SOI layers and resultant degradation of device performance. It is therefore essential to establish the quality of the silicon on the GPSOI substrate. MOS capacitor structures have been employed in this paper to characterize these GPSOI substrates for the first time. High quality MOS capacitor characteristics have been achieved with minority carrier lifetime of similar to 0.8 ms. These results show that the substrate is suitable for device manufacture with no degradation in the silicon due to stress or metallic contamination resulting from the inclusion of the underlying silicide layer.

Electrical methods of controlling bacterial adhesion and biofilm on device surfaces.

This review will summarize the significant body of research within the field of electrical methods of controlling the growth of microorganisms. We examine the progress from early work using current to kill bacteria in static fluids to more realistic treatment scenarios such as flow-through systems designed to imitate the human urinary tract. Additionally, the electrical enhancement of biocide and antibiotic efficacy will be examined alongside recent innovations including the biological applications of acoustic energy systems to prevent bacterial surface adherence. Particular attention will be paid to the electrical engineering aspects of previous work, such as electrode composition, quantitative electrical parameters and the conductive medium used. Scrutiny of published systems from an electrical engineering perspective will help to facilitate improved understanding of the methods, devices and mechanisms that have been effective in controlling bacteria, as well as providing insights and strategies to improve the performance of such systems and develop the next generation of antimicrobial bioelectric materials.

Electrical characterisation of liquid crystals at millimetre wavelengths using frequency selective surfaces

<br/><br/>Email<br/>Print<br/><br/> <br/><br/><br/><br/><br/><br/><br/><br/><br/><br/>The accurate measurement of the permittivity, loss tangent and dielectric anisotropy DC bias dependence for two different liquid crystal (LC) materials in the frequency range 140-165 GHz is described. The electrical characteristics are obtained by curve fitting computed transmission coefficients to the experimental spectral response of a new class of electronically reconfigurable frequency selective surface. The periodic structure is designed to yield bandpass filter characteristics with and without an applied bias control voltage in order to measure the tunability of the LC material which is inserted in a 705 µm-thick cavity.<br/>

The Islay wave power project: an engineering prospective

The design, construction and subsequent operation of the 75 kW oscillating water column wave power plant on the Isle of Islay has provided a significant insight into the practicality of wave power conversion. The development of wave power plant poses a significant design and construction challenge for not only civil but also mechanical and electrical engineers. The plant must withstand the immense forces imposed during storms, yet efficiently convert the slow cyclic motion of waves into a useful energy source such as electricity and do so at a price competitive with other forms of generation. In addition, the hostile marine environment hampers the construction process and the variability of the wave resource poses problems for electrical control and grid integration. Many sceptics consider wave power conversion to be too difficult, too expensive and too variable to justify the effort and expense necessary to develop this technology. However, the authors contend that with modular wave power systems developed from the practical experience gained with the Islay plant, wave power is a viable technology with a considerable world market potential. However, this technology is still at the early stages of development and will require the construction of a number of different prototypes before there is extensive commercial exploitation.

Monitoring electrical resistance of concretes containing alternative cementitious materials to assess their resistance to chloride penetration

This is an invited contribution in a special issue of the Journal of Cement and Concrete Composites

Transmission loss allocation in a deregulated electrical energy market

This paper presents a new method for transmission loss allocation in a deregulated electrical power market. The proposed method is based on physical flow through transmission lines. The contributions of individual loads to the line flows are used as basis for allocating transmission losses to different loads. With minimum assumptions, that sound to be reasonable and cannot be rejected, a novel loss allocation formula is derived. The assumptions made are: a number of currents sharing a transmission line distribute themselves over the cross section in the same manner; that distribution causes the minimum possible power loss. Application of the proposed method is straightforward. It requires only a solved power flow and any simple algorithm for power flow tracing. Both active and reactive powers are considered in the loss allocation procedure. Results of application show the accuracy of the proposed method compared with the commonly used procedures.

6-T SRAM cell design with nanoscale double-gate SOI MOSFETs: impact of source/drain engineering and circuit topology

The impact of source/drain engineering on the performance of a six-transistor (6-T) static random access memory (SRAM) cell, based on 22 nm double-gate (DG) SOI MOSFETs, has been analyzed using mixed-mode simulation, for three different circuit topologies for low voltage operation. The trade-offs associated with the various conflicting requirements relating to read/write/standby operations have been evaluated comprehensively in terms of eight performance metrics, namely retention noise margin, static noise margin, static voltage/current noise margin, write-ability current, write trip voltage/current and leakage current. Optimal design parameters with gate-underlap architecture have been identified to enhance the overall SRAM performance, and the influence of parasitic source/drain resistance and supply voltage scaling has been investigated. A gate-underlap device designed with a spacer-to-straggle (s/sigma) ratio in the range 2-3 yields improved SRAM performance metrics, regardless of circuit topology. An optimal two word-line double-gate SOI 6-T SRAM cell design exhibits a high SNM similar to 162 mV, I-wr similar to 35 mu A and low I-leak similar to 70 pA at V-DD = 0.6 V, while maintaining SNM similar to 30% V-DD over the supply voltage (V-DD) range of 0.4-0.9 V.

Source/drain extension region engineering in nanoscale double gate SOI MOSFETs: Novel design methodology for low-voltage analog applications

The present paper proposes for the first time, a novel design methodology based on the optimization of source/drain extension (SDE) regions to significantly improve the trade-off between intrinsic voltage gain (A(vo)) and cut-off frequency (f(T)) in nanoscale double gate (DG) devices. Our results show that an optimally designed 25 nm gate length SDE region engineered DG MOSFET operating at drain current of 10 mu A/mu m, exhibits up to 65% improvement in intrinsic voltage gain and 85% in cut-off frequency over devices designed with abrupt SIDE regions. The influence of spacer width, lateral source/drain doping gradient and symmetric as well as asymmetrically designed SDE regions on key analog figures of merit (FOM) such as transconductance (g(m)), transconductance-to-current ratio (g(m)/I-ds), Early voltage (V-EA), output conductance (g(ds)) and gate capacitances are examined in detail. The present work provides new opportunities for realizing future low-voltage/low-power analog circuits with nanoscale SDE engineered DG MOSFETs. (C) 2007 Elsevier B.V. All rights reserved.

Source/drain extension region engineering in FinFETs for low-voltage analog applications

In this letter, we propose a novel design methodology for engineering source/drain extension (SDE) regions to simultaneously improve intrinsic dc gain (A(vo)) and cutoff frequency (f(T)) of 25-nm gate-length FinFETs operated at low drain-current (I-ds = 10 mu A/mu m). SDE region optimization in 25-nm FinFETs results in exceptionally high values of Avo (similar to 45 dB) and f(T) (similar to 70 GHz), which is nearly 2.5 times greater when compared to devices designed with abrupt SDE regions. The influence of spacer width, lateral source/drain doping gradient, and the spacer-to-gradient ratio on key analog figures of merit is examined in detail. This letter provides new opportunities for realizing future low-voltage/low-power analog design with nanoscale SDE-engineered FinFETs.

Engineering source/drain extension regions in nanoscale double gate (DG) SOI MOSFETs: Analytical model and design considerations

In this paper, we propose for the first time, an analytical model for short channel effects in nanoscale source/drain extension region engineered double gate (DG) SOI MOSFETs. The impact of (i) lateral source/drain doping gradient (d), (ii) spacer width (s), (iii) spacer to doping gradient ratio (s/d) and (iv) silicon film thickness (T-si), on short channel effects - threshold voltage (V-th) and subthreshold slope (S), on-current (I-on), off-current (I-on) and I-on/I-off is extensively analysed by using the analytical model and 2D device simulations. The results of the analytical model confirm well with simulated data over the entire range of spacer widths, doping gradients and effective channel lengths. Results show that lateral source/drain doping gradient along with spacer width can not only effectively control short channel effects, thus presenting low off-current, but can also be optimised to achieve high values of on-currents. The present work provides valuable design insights in the performance of nanoscale DG Sol devices with optimal source/drain engineering and serves as a tool to optimise important device and technological parameters for 65 nm technology node and below. (c) 2006 Elsevier Ltd. All rights reserved.

Enhancing the teaching of professional practice and key skills in engineering through the use of computer animation

This paper presents some observations on how computer animation was used in the early years of a degree program in Electrical and Electronic Engineering to enhance the teaching of key skills and professional practice. This paper presents the results from two case studies. First, in a first year course which seeks to teach students how to manage and report on group projects in a professional way. Secondly, in a technical course on virtual reality, where the students are asked to use computer animation in a way that subliminally coerces them to come to terms with the fine detail of the mathematical principles that underlie 3D graphics, geometry, etc. as well as the most significant principles of computer architecture and software engineering. In addition, the findings reveal that by including a significant element of self and peer review processes into the assessment procedure students became more engaged with the course and achieved a deeper level of comprehension of the material in the course.