Hardware elliptic curve cryptographic processor over GF(p)

A novel hardware architecture for elliptic curve cryptography (ECC) over GF(p) is introduced. This can perform the main prime field arithmetic functions needed in these cryptosystems including modular inversion and multiplication. This is based on a new unified modular inversion algorithm that offers considerable improvement over previous ECC techniques that use Fermat's Little Theorem for this operation. The processor described uses a full-word multiplier which requires much fewer clock cycles than previous methods, while still maintaining a competitive critical path delay. The benefits of the approach have been demonstrated by utilizing these techniques to create a field-programmable gate array (FPGA) design. This can perform a 256-bit prime field scalar point multiplication in 3.86 ms, the fastest FPGA time reported to date. The ECC architecture described can also perform four different types of modular inversion, making it suitable for use in many different ECC applications. © 2006 IEEE.

Optimized bit level architectures for IIR filtering

Optimized circuits for implementing high-performance bit-parallel IIR filters are presented. Circuits constructed mainly from simple carry save adders and based on most-significant-bit (MSB) first arithmetic are described. Two methods resulting in systems which are 100% efficient in that they are capable of sampling data every cycle are presented. In the first approach the basic circuit is modified so that the level of pipelining used is compatible with the small, but fixed, latency associated with the computation in question. This is achieved through insertion of pipeline delays (half latches) on every second row of cells. This produces an area-efficient solution in which the throughput rate is determined by a critical path of 76 gate delays. A second approach combines the MSB first arithmetic methods with the scattered look-ahead methods. Important design issues are addressed, including wordlength truncation, overflow detection, and saturation.

Michel Foucault and Dorothy Smith in Case File Research: Strange Bedfellows or Complimentary Thinkers?

The aim of this article is to provide an exploration how the work of two theorists with notably different stances could be used effectively to enhance critical research methods in relation to the history of child welfare social work. The design and implementation of child welfare policies, practices and discourses could considerably benefit from a more historically well grounded scholarship that enables actors to connect their present concerns with the broader historical dynamics of social regulation. The article reports on how the work of Michel Foucault and Dorothy E. Smith might be considered in parallel as two different perspectives to the same scene in time and place. The differences and similarities in their approaches are explored with an emphasis on concepts most relevant to researching child welfare archives including discourse, text, the subject and power-knowledge. The article concludes with a commentary on further development to take forward this methodological analysis.

Berryman, Sexton and the Possibilities of Poetic Language

This paper examines a select number of poems by Middle Generation poets John Berryman and Anne Sexton in relation to questions of death, silence and the task that literature sets itself as understood in key works by Blanchot, Heidegger, and Levinas. Rather than recourse to the overtrodden critical path of confessional interpretations of their work, this paper connects Berryman’s The Dream Songs (1969) and two Sexton poems (‘Oh’ and ‘The Silence’) to the philosophical determinations of what it is language can say and what demands literature makes of the writer prepared to risk their own being in answer to its call. Central issues such as suicide and the originating silence of the work of art are intricately interwoven with Berryman’s and Sexton’s work. Leaving aside their biographies, and by approaching suicide as a philosophical problem with which their poetry wrestles, a restructured approach to their work becomes available. The impulse to suicide and the mental processes involved in considering and committing the act are instincts and responses located within an individual’s own psychology. For these writers particularly such issues are sited within a philosophical debate about language, what it can and cannot represent. If poetry articulates language’s argument about its own capability, it is the ideal forum for philosophical confrontations with the possibilities of existence as represented by the grave decision to take one’s own life. © The Author 2013.

Design of interlock-free combined allocators for Networks-on-Chip

This paper presents a thorough investigation of the combined allocator design for Networks-on-Chip (NoC). Particularly, we discuss the interlock of the combined NoC allocator, which is caused by the lock mechanism of priority updating between the local and global arbiters. Architectures and implementations of three interlock-free combined allocators are presented in detail. Their cost, critical path, as well as network level performance are demonstrated based on 65-nm standard cell technology.

A Unified Scheduler for Recursive and Task Dataflow Parallelism

Task dataflow languages simplify the specification of parallel programs by dynamically detecting and enforcing dependencies between tasks. These languages are, however, often restricted to a single level of parallelism. This language design is reflected in the runtime system, where a master thread explicitly generates a task graph and worker threads execute ready tasks and wake-up their dependents. Such an approach is incompatible with state-of-the-art schedulers such as the Cilk scheduler, that minimize the creation of idle tasks (work-first principle) and place all task creation and scheduling off the critical path. This paper proposes an extension to the Cilk scheduler in order to reconcile task dependencies with the work-first principle. We discuss the impact of task dependencies on the properties of the Cilk scheduler. Furthermore, we propose a low-overhead ticket-based technique for dependency tracking and enforcement at the object level. Our scheduler also supports renaming of objects in order to increase task-level parallelism. Renaming is implemented using versioned objects, a new type of hyper object. Experimental evaluation shows that the unified scheduler is as efficient as the Cilk scheduler when tasks have no dependencies. Moreover, the unified scheduler is more efficient than SMPSS, a particular implementation of a task dataflow language.

An Investigation towards colossal success of Larsen and Toubro Limited: Human resource management perspective

Larsen and Toubro (L&T) Limited is India’s largest construction conglomerate. L&T’s expertise is harnessed to execute high value projects that demand adherence to stringent timelines in a scenario where disparate disciplines of engineering are required to be coordinated on a critical path. However, no company can acquire such a feat without systematic management of its human resource. An investigation on the human resource management practices in orienting L&T’s success can help to identify some of the ethical human resource practices, especially in the context of Indian market. Accordingly, a well-designed employee satisfaction survey was conducted for assessment of the HRM practices being followed in L&T. Unlike other companies, L&T aims to meet the long-term needs of its employees rather than short-term needs. There were however few areas of concerns, such as yearly appraisal system and equality to treat the employees. It is postulated that the inequality to treat the male and female employees is primarily a typical stereotype due to the fact that construction is conventionally believed to be a male dominant activity. A periodic survey intended to provide 360° feedback system can help to avoid such irregularities. This study is thus expected to provide healthy practices of HRM to nurture the young talents of India. This may help them to evaluate their decisions by analyzing the complex relationship between HRM practices and output of an organization.

Secure Implementation in Production Economies

This paper shows that, in production economies, the generalized serial social choice functions defined by Shenker (1992) are securely implementable (in the sense of Saijo et al., 2007) and that they include the well-known fixed path social choice functions.

The impact of global routing on the performance of NoCs in FPGAs

With the over-provisioned routing resource on FPGA, the topology choice for NoC implementation on FPGA is more flexible than on ASIC. However, it is well understood that the global wire routing impacts the performance of NoC on FPGA because the topology is routed by using fixed routing fabric. An important question that arises is: will the benefit of diameter reduction by using a highly connective topology outweigh the impact of global routing? To answer this question, we investigate FPGA based packet switched NoC implementations with different sizes and topologies, and quantitatively measure the impact of global routing to each of these networks. The result shows that with sufficient routing resources on modern FPGA, the global routing is not on the critical path of the system, and thus is not a dominating factor for the performance of practical multi-hop NoC system. © 2011 IEEE.

Low-Power Process-Variation Tolerant Arithmetic Units Using Input-Based Elastic Clocking

In this paper we propose a design methodology for low-power high-performance, process-variation tolerant architecture for arithmetic units. The novelty of our approach lies in the fact that possible delay failures due to process variations and/or voltage scaling are predicted in advance and addressed by employing an elastic clocking technique. The prediction mechanism exploits the dependence of delay of arithmetic units upon input data patterns and identifies specific inputs that activate the critical path. Under iso-yield conditions, the proposed design operates at a lower scaled down Vdd without any performance degradation, while it ensures a superlative yield under a design style employing nominal supply and transistor threshold voltage. Simulation results show power savings of upto 29%, energy per computation savings of upto 25.5% and yield enhancement of upto 11.1% compared to the conventional adders and multipliers implemented in the 70nm BPTM technology. We incorporated the proposed modules in the execution unit of a five stage DLX pipeline to measure performance using SPEC2000 benchmarks [9]. Maximum area and throughput penalty obtained were 10% and 3% respectively.

A multi-capability sensor for hydrocarbons, synthetic-based fluids and heavy metals:Applications for environmental monitoring during removal of drill cuttings piles

As part of any drilling cuttings pile removal process the requirement for monitoring the release of contaminants into the marine environment will be critical. Traditional methods for such monitoring involve taking samples for laboratory analysis. This process is time consuming and only provides data on spot samples taken from a limited number of locations and time frames. Such processes, therefore, offer very restricted information. The need for improved marine sensors for monitoring contaminants is established. We report here the development and application of a multi-capability optical sensor for the real-time in situ monitoring of three key marine environmental and offshore/oil parameters: hydrocarbons, synthetic-based fluids and heavy metal concentrations. The use of these sensors will be a useful tool for real-time in situ environmental monitoring during the process of decommissioning offshore structures. Multi-capability array sensors could also provide information on the dispersion of contamination from drill cuttings piles either while they are in situ or during their removal.

Exploiting dynamic timing margins in microprocessors for frequency-over-scaling with instruction-based clock adjustment

Static timing analysis provides the basis for setting the clock period of a microprocessor core, based on its worst-case critical path. However, depending on the design, this critical path is not always excited and therefore dynamic timing margins exist that can theoretically be exploited for the benefit of better speed or lower power consumption (through voltage scaling). This paper introduces predictive instruction-based dynamic clock adjustment as a technique to trim dynamic timing margins in pipelined microprocessors. To this end, we exploit the different timing requirements for individual instructions during the dynamically varying program execution flow without the need for complex circuit-level measures to detect and correct timing violations. We provide a design flow to extract the dynamic timing information for the design using post-layout dynamic timing analysis and we integrate the results into a custom cycle-accurate simulator. This simulator allows annotation of individual instructions with their impact on timing (in each pipeline stage) and rapidly derives the overall code execution time for complex benchmarks. The design methodology is illustrated at the microarchitecture level, demonstrating the performance and power gains possible on a 6-stage OpenRISC in-order general purpose processor core in a 28nm CMOS technology. We show that employing instruction-dependent dynamic clock adjustment leads on average to an increase in operating speed by 38% or to a reduction in power consumption by 24%, compared to traditional synchronous clocking, which at all times has to respect the worst-case timing identified through static timing analysis.