Even order harmonic Series-L/Parallel-Tuned Class-E frequency multiplier

In this brief, we propose a new Class-E frequency multiplier based on the recently introduced Series-L/Parallel-Tuned Class-E amplifier. The proposed circuit produces even-order output harmonics. Unlike previously reported solutions the proposed circuit can operate under 50% duty ratio which minimizes the conduction losses. The circuit also offers the possibility for increased maximum operating frequency, reduced peak switch voltage, higher load resistance and inherent bond wire absorption; all potentially useful in monolithic microwave integrated circuit implementations. In addition, the circuit topology suggested large transistors with high output capacitances can be deployed. Theoretical design equations are given and the predictions made using these are shown to agree with harmonic balance circuit simulation results.

Multiplier-less realization of a poly-phase filter using LUT-based FPGAs

In DSP applications such as fixed transforms and filtering, the full flexibility of a general-purpose multiplier is not required and only a limited range of values is needed on one of the multiplier inputs. A new design technique has been developed for deriving multipliers that operate on a limited range of multiplicands. This can be used to produce FPGA implementations of DSP systems where area is dramatically improved. The paper describes the technique and its application to the design of a poly-phase filter on a Virtex FPGA. A 62% area reduction and 7% speed increase is gained when compared to an equivalent design using general purpose multipliers. It is also compared favourably to other known fixed coefficient approaches.

When is the second local multiplier algebra of a C*-algebra equal to the first?

We discuss necessary as well as sufficient conditions for the second iterated local multiplier algebra of a separable C*-algebra to agree with the first.

COMPLETELY ITERATIVE, PIPELINED MULTIPLIER ARRAY SUITABLE FOR VLSI.

A pipelined array multiplier which has been derived by applying 'systolic array' principles at the bit level is described. Attention is focused on a circuit which is used to multiply streams of parallel unsigned data. Then an algorithm is given which demonstrates that, with only a simple modification to the basic cell, the same array can cope with two's complement numbers. The resulting structure has a number of features whch make it attractive to LSI and VLSI. These include regularity and modularity.

Targeting FPGA DSP Slices for a Large Integer Multiplier for Integer Based FHE

Homomorphic encryption offers potential for secure cloud computing. However due to the complexity of homomorphic encryption schemes, performance of implemented schemes to date have been unpractical. This work investigates the use of hardware, specifically Field Programmable Gate Array (FPGA) technology, for implementing the building blocks involved in somewhat and fully homomorphic encryption schemes in order to assess the practicality of such schemes. We concentrate on the selection of a suitable multiplication algorithm and hardware architecture for large integer multiplication, one of the main bottlenecks in many homomorphic encryption schemes. We focus on the encryption step of an integer-based fully homomorphic encryption (FHE) scheme. We target the DSP48E1 slices available on Xilinx Virtex 7 FPGAs to ascertain whether the large integer multiplier within the encryption step of a FHE scheme could fit on a single FPGA device. We find that, for toy size parameters for the FHE encryption step, the large integer multiplier fits comfortably within the DSP48E1 slices, greatly improving the practicality of the encryption step compared to a software implementation. As multiplication is an important operation in other FHE schemes, a hardware implementation using this multiplier could also be used to improve performance of these schemes.

Using signed digit arithmetic for low-power multiplication

Hardware implementations of arithmetic operators using signed digit arithmetic have lost some of their earlier popularity. However, SD is revisited and used to realise an efficient radix-16 generic multiplier, which has particular potential for low-power implementation. The SD multiplier algorithm reduces the number of partial products to as much as 1/4, and in initial tests reduces the estimated power consumption to only about 50% of that of the Booth multiplier. It is different from other previous high-radix methods in that it employs a novel method to generate its partial products with zero arithmetic logic.

Maximal C*-algebras of quotients and injective envelopes of C*-algebras

A new C*-enlargement of a C*-algebra A nested between the local multiplier algebra of A and its injective envelope is introduced. Various aspects of this maximal C*-algebra of quotients are studied, notably in the setting of AW*-algebras. As a by-product we obtain a new example of a type I C*-algebra such that its second iterated local multiplier algebra is strictly larger than its local multiplier algebra.

Sheaves of C*-algebras

We develop the basics of a theory of sheaves of C*-algebras and, in particular, compare it to the existing theory of C*-bundles. The details of two fundamental examples, the local multiplier sheaf and the injective envelope sheaf, are discussed.

Compactness properties of operator multipliers

We continue the study of multidimensional operator multipliers initiated in~cite{jtt}. We introduce the notion of the symbol of an operator multiplier. We characterise completely compact operator multipliers in terms of their symbol as well as in terms of approximation by finite rank multipliers. We give sufficient conditions for the sets of compact and completely compact multipliers to coincide and characterise the cases where an operator multiplier in the minimal tensor product of two C*-algebras is automatically compact. We give a description of multilinear modular completely compact completely bounded maps defined on the direct product of finitely many copies of the C*-algebra of compact operators in terms of tensor products, generalising results of Saar