Analysis and Design of Class-E3F and Transmission-Line Class-E3F2 Power Amplifiers

In this paper, analysis and synthesis approach for two new variants within the Class-EF power amplifier (PA) family is elaborated. These amplifiers are classified here as Class-E3 F2 and transmission-line (TL) Class-E3 F 2. The proposed circuits offer means to alleviate some of the major issues faced by existing topologies such as substantial power losses due to the parasitic resistance of the large inductor in the Class-EF load network and deviation from ideal Class-EF operation due to the effect of device output inductance at high frequencies. Both lumped-element and transmission-line load networks for the Class-E 3 F PA are described. The load networks of the Class-E3 F and TL Class-E 3 F2amplifier topologies developed in this paper simultaneously satisfy the Class-EF optimum impedance requirements at fundamental frequency, second, and third harmonics as well as simultaneously providing matching to the circuit optimum load resistance for any prescribed system load resistance. Optimum circuit component values are analytically derived and validated by harmonic balance simulations. Trade-offs between circuit figures of merit and component values with some practical limitations being considered are discussed. © 2010 IEEE.

Analysis of Extended Partial Least Squares for Monitoring Large-Scale Processes

This paper theoretically analysis the recently proposed "Extended Partial Least Squares" (EPLS) algorithm. After pointing out some conceptual deficiencies, a revised algorithm is introduced that covers the middle ground between Partial Least Squares and Principal Component Analysis. It maximises a covariance criterion between a cause and an effect variable set (partial least squares) and allows a complete reconstruction of the recorded data (principal component analysis). The new and conceptually simpler EPLS algorithm has successfully been applied in detecting and diagnosing various fault conditions, where the original EPLS algorithm did only offer fault detection.

Analysis of Load Impact on Small-signal Stability based on Load Active Power Sensitivity

While load flow conditions vary with different loads, the small-signal stability of the entire system is closely related with to the locations, capacities and models of loads. In this paper, load impacts with different capacities and models on the small-signal stability are analysed. In the real large-scale power system case, the load sensitivity which denotes the sensitivity of the eigenvalue with respect to the load active power is introduced and applied to rank the loads. The loads with high sensitivity are also considered.

COMPLETELY ITERATIVE, PIPELINED MULTIPLIER ARRAY SUITABLE FOR VLSI.

A pipelined array multiplier which has been derived by applying 'systolic array' principles at the bit level is described. Attention is focused on a circuit which is used to multiply streams of parallel unsigned data. Then an algorithm is given which demonstrates that, with only a simple modification to the basic cell, the same array can cope with two's complement numbers. The resulting structure has a number of features whch make it attractive to LSI and VLSI. These include regularity and modularity.

BIT-LEVEL SYSTOLIC ARRAY CIRCUIT FOR MATRIX VECTOR MULTIPLICATION.

A bit-level systolic array for computing matrix x vector products is described. The operation is carried out on bit parallel input data words and the basic circuit takes the form of a 1-bit slice. Several bit-slice components must be connected together to form the final result, and authors outline two different ways in which this can be done. The basic array also has considerable potential as a stand-alone device, and its use in computing the Walsh-Hadamard transform and discrete Fourier transform operations is briefly discussed.

Coordination chemistry for information acquisition and processing

In the 21st century, information has become the most valuable resource that is available to modern societies. Thus, great efforts have been made to develop new information processing and storage techniques. Chemistry can offer a wide variety of computing paradigms that are closely related to the natural processes found in living organisms (e.g., in the nervous systems of animals). Moreover, these phenomena cannot be reproduced easily by solely using silicon-based technology. Other great advantages of molecular-scale systems include their simplicity and the diversity of interactions that occur among them. Thus, devices constructed using chemical entities may be programmed to deal with different information carriers (photons, electrons, ions, and molecules), possibly surpassing the capabilities of classic electronic circuits.

Hardware Performance Analysis of the SHACAL-2 Encryption Algorithm

A hardware performance analysis of the SHACAL-2 encryption algorithm is presented in this paper. SHACAL-2 was one of four symmetric key algorithms chosen in the New European Schemes for Signatures, Integrity and Encryption (NESSIE) initiative in 2003. The paper describes a fully pipelined encryption SHACAL-2 architecture implemented on a Xilinx Field Programmable Gate Array (FPGA) device that achieves a throughput of over 25 Gbps. This is the fastest private key encryption algorithm architecture currently available. The SHACAL-2 decryption algorithm is also defined in the paper as it was not provided in the NESSIE submission.

Scaling issues for analogue circuits using Double Gate SOI transistors

This work presents a systematic analysis on the impact of source-drain engineering using gate

Design and analysis of dual-rail circuits for security applications

Dual-rail encoding, return-to-spacer protocol, and hazard-free logic can be used to resist power analysis attacks by making energy consumed per clock cycle independent of processed data. Standard dual-rail logic uses a protocol with a single spacer, e.g., all-zeros, which gives rise to energy balancing problems. We address these problems by incorporating two spacers; the spacers alternate between adjacent clock cycles. This guarantees that all gates switch in every clock cycle regardless of the transmitted data values. To generate these dual-rail circuits, an automated tool has been developed. It is capable of converting synchronous netlists into dual-rail circuits and it is interfaced to industry CAD tools. Dual-rail and single-rail benchmarks based upon the advanced encryption standard (AES) have been simulated and compared in order to evaluate the method and the tool.

A Tunable Encryption Scheme and Analysis of Fast Selective Encryption for CAVLC and CABAC in H.264/AVC

Recently, two fast selective encryption methods for context-adaptive variable length coding and context-adaptive binary arithmetic coding in H.264/AVC were proposed by Shahid et al. In this paper, it was demonstrated that these two methods are not as efficient as only encrypting the sign bits of nonzero coefficients. Experimental results showed that without encrypting the sign bits of nonzero coefficients, these two methods can not provide a perceptual scrambling effect. If a much stronger scrambling effect is required, intra prediction modes, and the sign bits of motion vectors can be encrypted together with the sign bits of nonzero coefficients. For practical applications, the required encryption scheme should be customized according to a user's specified requirement on the perceptual scrambling effect and the computational cost. Thus, a tunable encryption scheme combining these three methods is proposed for H.264/AVC. To simplify its implementation and reduce the computational cost, a simple control mechanism is proposed to adjust the control factors. Experimental results show that this scheme can provide different scrambling levels by adjusting three control factors with no or very little impact on the compression performance. The proposed scheme can run in real-time and its computational cost is minimal. The security of the proposed scheme is also discussed. It is secure against the replacement attack when all three control factors are set to one.

Bit erasure analysis of binary adders in quantum-dot cellular automata

As a post-CMOS technology, the incipient Quantum-dot Cellular Automata technology has various advantages. A key aspect which makes it highly desirable is low power dissipation. One method that is used to analyse power dissipation in QCA circuits is bit erasure analysis. This method has been applied to analyse previously proposed QCA binary adders. However, a number of improved QCA adders have been proposed more recently that have only been evaluated in terms of area and speed. As the three key performance metrics for QCA circuits are speed, area and power, in this paper, a bit erasure analysis of these adders will be presented to determine their power dissipation. The adders to be analysed are the Carry Flow Adder (CFA), Brent-Kung Adder (B-K), Ladner-Fischer Adder (L-F) and a more recently developed area-delay efficient adder. This research will allow for a more comprehensive comparison between the different QCA adder proposals. To the best of the authors' knowledge, this is the first time power dissipation analysis has been carried out on these adders.

Communication Nonlinearities Techniques for Analysis of Passive Intermodulation

The X-parameter based nonlinear modelling tools have been adopted as the foundation for the advanced methodology
of experimental characterisation and design of passive nonlinear devices. Based upon the formalism of the Xparameters,
it provides a unified framework for co-design of antenna beamforming networks, filters, phase shifters and
other passive and active devices of RF front-end, taking into account the effect of their nonlinearities. The equivalent
circuits of the canonical elements are readily incorporated in the models, thus enabling evaluation of PIM effect on the
performance of individual devices and their assemblies. An important advantage of the presented methodology is its
compatibility with the industry-standard established commercial RF circuit simulator Agilent ADS.
The major challenge in practical implementation of the proposed approach is concerned with experimental retrieval of the X-parameters for canonical passive circuit elements. To our best knowledge commercial PIM testers and practical laboratory test instruments are inherently narrowband and do not allow for simultaneous vector measurements at the PIM and harmonic frequencies. Alternatively, existing nonlinear vector analysers (NVNA) support X-parameter measurements in a broad frequency bands with a range of stimuli, but their dynamic range is insufficient for the PIM characterisation in practical circuits. Further opportunities for adaptation of the X-parameters methodology to the PIM
characterisation of passive devices using the existing test instruments are explored.