Non-equilibrium induction of tin in germanium: towards direct bandgap Ge1-xSnx nanowires

The development of non-equilibrium group IV nanoscale alloys is critical to achieving new functionalities, such as the formation of a direct bandgap in a conventional indirect bandgap elemental semiconductor. Here, we describe the fabrication of uniform diameter, direct bandgap Ge1-xSnx alloy nanowires, with a Sn incorporation up to 9.2[thinsp]at.%, far in excess of the equilibrium solubility of Sn in bulk Ge, through a conventional catalytic bottom-up growth paradigm using noble metal and metal alloy catalysts. Metal alloy catalysts permitted a greater inclusion of Sn in Ge nanowires compared with conventional Au catalysts, when used during vapour-liquid-solid growth. The addition of an annealing step close to the Ge-Sn eutectic temperature (230[thinsp][deg]C) during cool-down, further facilitated the excessive dissolution of Sn in the nanowires. Sn was distributed throughout the Ge nanowire lattice with no metallic Sn segregation or precipitation at the surface or within the bulk of the nanowires. The non-equilibrium incorporation of Sn into the Ge nanowires can be understood in terms of a kinetic trapping model for impurity incorporation at the triple-phase boundary during growth.

Simulation of multigate SOI transistors with silicon, germanium and III-V channels

In this work by employing numerical three-dimensional simulations we study the electrical performance and short channel behavior of several multi-gate transistors based on advanced SOI technology. These include FinFETs, triple-gate and gate-all-around nanowire FETs with different channel material, namely Si, Ge, and III-V compound semiconductors, all most promising candidates for future nanoscale CMOS technologies. Also, a new type of transistor called “junctionless nanowire transistor” is presented and extensive simulations are carried out to study its electrical characteristics and compare with the conventional inversion- and accumulation-mode transistors. We study the influence of device properties such as different channel material and orientation, dimensions, and doping concentration as well as quantum effects on the performance of multi-gate SOI transistors. For the modeled n-channel nanowire devices we found that at very small cross sections the nanowires with silicon channel are more immune to short channel effects. Interestingly, the mobility of the channel material is not as significant in determining the device performance in ultrashort channels as other material properties such as the dielectric constant and the effective mass. Better electrostatic control is achieved in materials with smaller dielectric constant and smaller source-to-drain tunneling currents are observed in channels with higher transport effective mass. This explains our results on Si-based devices. In addition to using the commercial TCAD software (Silvaco and Synopsys TCAD), we have developed a three-dimensional Schrödinger-Poisson solver based on the non-equilibrium Green’s functions formalism and in the framework of effective mass approximation. This allows studying the influence of quantum effects on electrical performance of ultra-scaled devices. We have implemented different mode-space methodologies in our 3D quantum-mechanical simulator and moreover introduced a new method to deal with discontinuities in the device structures which is much faster than the coupled-mode-space approach.