7 resultados para electrical engineering

em Biblioteca Digital da Produção Intelectual da Universidade de São Paulo


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This paper discusses some aspects related to Wireless Sensor Networks over the IEEE 802.15.4 standard, and proposes, for the very first time, a mesh network topology with geographic routing integrated to the open Freescale protocol (SMAC - Simple Medium Access Control). For this is proposed the SMAC routing protocol. Before this work the SMAC protocol was suitable to perform one hop communications only. However, with the developed mechanisms, it is possible to use multi-hop communication. Performance results from the implemented protocol are presented and analyzed in order to define important requirements for wireless sensor networks, such as robustness, self-healing property and low latency. (c) 2011 Elsevier Ltd. All rights reserved.

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The influence of deposition parameters, namely polymer concentration and pH of the deposition solution, cleaning, and drying steps on the morphology and electrical characteristics of polyaniline and sulfonated polystyrene (PANI/PSS) nanostructured films deposited by the self-assembly technique is evaluated by UV-Vis spectroscopy, optical and atomic force microscopy, and electrical resistance measurements. It is found that stirring the cleaning solution during the cleaning step is crucial for obtaining homogenous films. Stirring of the cleaning solution also influences the amount of PANI adsorbed in the films. In this regard, the drying process seems to be less critical since PANI amount and film thickness are similar in films dried with N-2 flow or with an absorbent tissue. It is observed, however, that drying with N-2 flow results in rougher films. As an additional point, an assessment of the influence of the deposition method (manual versus mechanical) on the film characteristics was carried out. A significant difference on the amount of PANI and film thickness between films prepared by different human operators and by a homemade mechanical device was observed. The variability in film thickness and PANI adsorbed amount is smaller in films mechanically assembled. (c) 2007 Elsevier B.V. All rights reserved.

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Ion implantation of metal species into insulators provides a tool for the formation of thin, electrically conducting, surface layers with experimenter-controlled resistivity. High energy implantation of Pt and Ti into alumina accelerator components has been successfully employed to control high voltage surface breakdown in a number of cases. In the work described here we have carried out some basic investigations related to the origin of this phenomenon. By comparison of the results of alumina implanted with Ti at 75 keV with the results of prior investigations of polymers implanted with Pt at 49 eV and Au at 67 eV, we describe a physical model of the effect based on percolation theory and estimate the percolation parameters for the Ti-alumina composite. We estimate that the percolation dose threshold is about 4 x 10(16) cm(-2) and the maximum dose for which the system remains an insulator-conductor composite is about 10 x 10(16) cm(-2). The saturation electrical conductivity is estimated to be about 50 S/m. We conclude that the observed electrical conductivity properties of Ti-implanted alumina can be satisfactorily described by percolation theory. (C) 2012 American Institute of Physics. [http://dx.doi.org/10.1063/1.3697900]

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The physical origins of the magnetic properties of nonoriented electrical steels; its relations to microstructural features like grain size, nonmetallic inclusions, dislocation density distribution, crystallographic texture, and residual stresses; and its processing by cold rolling and annealing are overviewed, using quantitative relations whenever available.

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Electrical impedance tomography (EIT) is an imaging technique that attempts to reconstruct the impedance distribution inside an object from the impedance between electrodes placed on the object surface. The EIT reconstruction problem can be approached as a nonlinear nonconvex optimization problem in which one tries to maximize the matching between a simulated impedance problem and the observed data. This nonlinear optimization problem is often ill-posed, and not very suited to methods that evaluate derivatives of the objective function. It may be approached by simulated annealing (SA), but at a large computational cost due to the expensive evaluation process of the objective function, which involves a full simulation of the impedance problem at each iteration. A variation of SA is proposed in which the objective function is evaluated only partially, while ensuring boundaries on the behavior of the modified algorithm.

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The interpretation of the effect of plastic deformation on the calculated excess loss component (anomalous-loss) supports the concept of loss separation. Magnetic losses and Barkhausen noise of nonoriented electrical steel sheets were measured on Epstein strips taken from a single coil of 0.8% Si nonoriented electrical steel. Sheets were extracted in the annealed condition, without any skin pass and with a grain size of 18 mu m. This material was cold rolled in order to obtain sets of samples with true strain from 2% up to 29%. X-ray diffraction was used to estimate the dislocation density. The analysis of magnetic properties was performed by Barkhausen noise measurements and also by analyzing the hysteresis loops obtained from Epstein frame measurements for different inductions and different frequencies (including the quasi-static regime for hysteresis loss measurements). These data allowed us to observe that most of the well known total loss increase with plastic deformation is due to an increase in the hysteresis loss component, while excess loss decreases to become negligible. This behavior can be explained if it is assumed that the plastic deformation lead to an increase in the number of domain walls per unit volume, thereby decreasing the excess loss. Barkhausen peak area increases with plastic deformation, reproducing results taken from samples of different silicon content.

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The floating-body-RAM sense margin and retention-time dependence on the gate length is investigated in UTBOX devices using BJT programming combined with a positive back bias (so-called V th feedback). It is shown that the sense margin and the retention time can be kept constant versus the gate length by using a positive back bias. Nevertheless, below a critical L, there is no room for optimization, and the memory performances suddenly drop. The mechanism behind this degradation is attributed to GIDL current amplification by the lateral bipolar transistor with a narrow base. The gate length can be further scaled using underlap junctions.