Epothilone-d rescues cognition and attenuates alzheimer’s disease-like pathology in APP/PS1 mice

AIMS: Cognitive decline in Alzheimer's disease (AD) patients has been linked to synaptic damage and neuronal loss. Hyperphosphorylation of tau protein destabilizes microtubules leading to the accumulation of autophagy/vesicular material and the generation of dystrophic neurites, thus contributing to axonal/synaptic dysfunction. In this study, we analyzed the effect of a microtubule-stabilizing compound in the progression of the disease in the hippocampus of APP751SL/PS1M146L transgenic model. METHODS: APP/PS1 mice (3 month-old) were treated with a weekly intraperitoneal injection of 2 mg/kg epothilone-D (Epo-D) for 3 months. Vehicle-injected animals were used as controls. Mice were tested on the Morris water maze, Y-maze and object-recognition tasks for memory performance. Abeta, AT8, ubiquitin and synaptic markers levels were analyzed by Western-blots. Hippocampal plaque, synaptic and dystrophic loadings were quantified by image analysis after immunohistochemical stainings. RESULTS: Epo-D treated mice exhibited a significant improvement in the memory tests compared to controls. The rescue of cognitive deficits was associated to a significant reduction in the AD-like hippocampal pathology. Levels of Abeta, APP and ubiquitin were significantly reduced in treated animals. This was paralleled by a decrease in the amyloid burden, and more importantly, in the plaque-associated axonal dystrophy pathology. Finally, synaptic levels were significantly restored in treated animals compared to controls. CONCLUSION: Epo-D treatment promotes synaptic and spatial memory recovery, reduces the accumulation of extracellular Abeta and the associated neuritic pathology in the hippocampus of APP/PS1 model. Therefore, microtubule stabilizing drugs could be considered therapeutical candidates to slow down AD progression. Supported by FIS-PI12/01431 and PI15/00796 (AG),FIS-PI12/01439 and PI15/00957(JV)

Improvements in Hardware Transactional Memory for GPU Architectures

In the multi-core CPU world, transactional memory (TM)has emerged as an alternative to lock-based programming for thread synchronization. Recent research proposes the use of TM in GPU architectures, where a high number of computing threads, organized in SIMT fashion, requires an effective synchronization method. In contrast to CPUs, GPUs offer two memory spaces: global memory and local memory. The local memory space serves as a shared scratch-pad for a subset of the computing threads, and it is used by programmers to speed-up their applications thanks to its low latency. Prior work from the authors proposed a lightweight hardware TM (HTM) support based in the local memory, modifying the SIMT execution model and adding a conflict detection mechanism. An efficient implementation of these features is key in order to provide an effective synchronization mechanism at the local memory level. After a quick description of the main features of our HTM design for GPU local memory, in this work we gather together a number of proposals designed with the aim of improving those mechanisms with high impact on performance. Firstly, the SIMT execution model is modified to increase the parallelism of the application when transactions must be serialized in order to make forward progress. Secondly, the conflict detection mechanism is optimized depending on application characteristics, such us the read/write sets, the probability of conflict between transactions and the existence of read-only transactions. As these features can be present in hardware simultaneously, it is a task of the compiler and runtime to determine which ones are more important for a given application. This work includes a discussion on the analysis to be done in order to choose the best configuration solution.

Insights into the Fallback Path of Best-Effort Hardware Transactional Memory Systems

Current industry proposals for Hardware Transactional Memory (HTM) focus on best-effort solutions (BE-HTM) where hardware limits are imposed on transactions. These designs may show a significant performance degradation due to high contention scenarios and different hardware and operating system limitations that abort transactions, e.g. cache overflows, hardware and software exceptions, etc. To deal with these events and to ensure forward progress, BE-HTM systems usually provide a software fallback path to execute a lock-based version of the code. In this paper, we propose a hardware implementation of an irrevocability mechanism as an alternative to the software fallback path to gain insight into the hardware improvements that could enhance the execution of such a fallback. Our mechanism anticipates the abort that causes the transaction serialization, and stalls other transactions in the system so that transactional work loss is mini- mized. In addition, we evaluate the main software fallback path approaches and propose the use of ticket locks that hold precise information of the number of transactions waiting to enter the fallback. Thus, the separation of transactional and fallback execution can be achieved in a precise manner. The evaluation is carried out using the Simics/GEMS simulator and the complete range of STAMP transactional suite benchmarks. We obtain significant performance benefits of around twice the speedup and an abort reduction of 50% over the software fallback path for a number of benchmarks.

Energy Efficiency of Software Transactional Memory in a Heterogeneous Architecture

Hardware vendors make an important effort creating low-power CPUs that keep battery duration and durability above acceptable levels. In order to achieve this goal and provide good performance-energy for a wide variety of applications, ARM designed the big.LITTLE architecture. This heterogeneous multi-core architecture features two different types of cores: big cores oriented to performance and little cores, slower and aimed to save energy consumption. As all the cores have access to the same memory, multi-threaded applications must resort to some mutual exclusion mechanism to coordinate the access to shared data by the concurrent threads. Transactional Memory (TM) represents an optimistic approach for shared-memory synchronization. To take full advantage of the features offered by software TM, but also benefit from the characteristics of the heterogeneous big.LITTLE architectures, our focus is to propose TM solutions that take into account the power/performance requirements of the application and what it is offered by the architecture. In order to understand the current state-of-the-art and obtain useful information for future power-aware software TM solutions, we have performed an analysis of a popular TM library running on top of an ARM big.LITTLE processor. Experiments show, in general, better scalability for the LITTLE cores for most of the applications except for one, which requires the computing performance that the big cores offer.

HPC Accelerators with 3D Memory

After a decade evolving in the High Performance Computing arena, GPU-equipped supercomputers have con- quered the top500 and green500 lists, providing us unprecedented levels of computational power and memory bandwidth. This year, major vendors have introduced new accelerators based on 3D memory, like Xeon Phi Knights Landing by Intel and Pascal architecture by Nvidia. This paper reviews hardware features of those new HPC accelerators and unveils potential performance for scientific applications, with an emphasis on Hybrid Memory Cube (HMC) and High Bandwidth Memory (HBM) used by commercial products according to roadmaps already announced.