Latency, Power and Performance Trade-offs in Network-on-Chips by Link Microarchitecture Exploration

This paper presents a power, latency and throughput trade-off study on NoCs by varying microarchitectural (e.g. pipelining) and circuit level (e.g. frequency and voltage) parameters. We change pipelining depth, operating frequency and supply voltage for 3 example NoCs - 16 node 2D Torus, Tree network and Reduced 2D Torus. We use an in-house NoC exploration framework capable of topology generation and comparison using parameterized models of Routers and links developed in SystemC. The framework utilizes interconnect power and delay models from a low-level modelling tool called Intacte[1]1. We find that increased pipelining can actually reduce latency. We also find that there exists an optimal degree of pipelining which is the most energy efficient in terms of minimizing energy-delay product.

Wideband acoustic absorption characteristics of rubberized coir for underwater applications

Reflection and transmission coefficients of rubberized coir pads over the frequency band 200 kHz to 4 MHz are presented in this Paper. These results are compared with those reported for neoprene, paraffin wax, rubber car mat and plastic door mat1. The rubberized coir pads were found to possess wideband absorption characteristics. It has been experimentally found that 0.05 m thick coir pads have almost 100% absorption in the frequency range 800 kHz-3 MHz with a maximum at 2.35 MHz. We have used this material for lining the water tank for underwater acoustic studies.

Underwater Sustainability of the ``Cassie'' State of Wetting

A rough hydrophobic surface when immersed in water can result in a ``Cassie'' state of wetting in which the water is in contact with both the solid surface and the entrapped air. The sustainability of the entrapped air on such surfaces is important for underwater applications such as reduction of flow resistance in microchannels and drag reduction of submerged bodies such as hydrofoils. We utilize an optical technique based oil total internal reflection of light at the water-air interface to quantify the spatial distribution of trapped air oil such a surface and its variation with immersion time. With this technique, we evaluate the sustainability of the Cassie state on hydrophobic surfaces with four different kinds of textures. The textures studied are regular arrays of pillars, ridges, and holes that were created in silicon by a wet etching technique, and also a texture of random craters that was obtained through electrodischarge machining of aluminum. These surfaces were rendered hydrophobic with a self-assembled layer Of fluorooctyl trichlorosilane. Depending on the texture, the size and shape of the trapped air pockets were found to vary. However, irrespective of the texture, both the size and the number of air pockets were found to decrease with time gradually and eventually disappear, suggesting that the sustainability of the ``Cassie'' state is finite for all the microstructures Studied. This is possibly due to diffusion of air from the trapped air pockets into the water. The time scale for disappearance of air pockets was found to depend on the kind of microstructure and the hydrostatic pressure at the water-air interface. For the surface with a regular array of pillars, the air pockets were found to be in the form of a thin layer perched on top of the pillars with a large lateral extent compared to the spacing between pillars. For other surfaces studied, the air pockets are smaller and are of the same order as the characteristic length scale of the texture. Measurements for the surface with holes indicate that the time for air-pocket disappearance reduces as the hydrostatic pressure is increased.

Synthesis and exploration of novel curcumin analogues as anti-malarial agents

Curcumin, a major yellow pigment and active component of turmeric, has been shown to possess anti-inflammatory and anti-cancer activities. Recent studies have indicated that curcumin inhibits chloroquine-sensitive (CQ-S) and chloroquine-resistant (CQ-R) Plasmodium falciparum growth in culture with an IC50 of not, vert, similar3.25 μM (MIC = 13.2 μM) and IC50 4.21 μM (MIC = 14.4 μM), respectively. In order to expand their potential as anti-malarials a series of novel curcumin derivatives were synthesized and evaluated for their ability to inhibit P. falciparum growth in culture. Several curcumin analogues examined show more effective inhibition of P. falciparumgrowth than curcumin. The most potent curcumin compounds 3, 6, and 11 were inhibitory for CQ-S P. falciparum at IC50 of 0.48, 0.87, 0.92 μM and CQ-R P. falciparum at IC50 of 0.45 μM, 0.89, 0.75 μM, respectively. Pyrazole analogue of curcumin (3) exhibited sevenfold higher anti-malarial potency against CQ-S and ninefold higher anti-malarial potency against CQ-R. Curcumin analogues described here represent a novel class of highly selective P. falciparum inhibitors and promising candidates for the design of novel anti-malarial agents.

Synthesis and exploration of novel curcumin analogues as anti-malarial agents

Curcumin, a major yellow pigment and active component of turmeric, has been shown to possess anti-inflammatory and anti-cancer activities. Recent studies have indicated that curcumin inhibits chloroquine-sensitive (CQ-S) and chloroquine-resistant (CQ-R) Plasmodium falciparum growth in culture with an IC50 of similar to 3.25 mu M (MIC = 13.2 mu M) and IC50 4.21 mu M (MIC = 14.4 mu M), respectively. In order to expand their potential as anti-malarials a series of novel curcumin derivatives were synthesized and evaluated for their ability to inhibit P. falciparum growth in culture. Several curcumin analogues examined show more effective inhibition of P. falciparum growth than curcumin. The most potent curcumin compounds 3, 6, and 11 were inhibitory for CQ-S P. falciparum at IC50 of 0.48, 0.87, 0.92 mu M and CQ-R P. falcipartan at IC50 of 0.45 mu M, 0.89, 0.75 mu M, respectively. Pyrazole analogue of curcumin (3) exhibited sevenfold higher anti-malarial potency against CQ-S and ninefold higher anti-malarial potency against CQ-R. Curcumin analogues described here represent a novel class of highly selective P. falcipartan inhibitors and promising candidates for the design of novel anti-malarial agents. (C) 2007 Elsevier Ltd. All rights reserved.

Methyl ethyl ketone plus water plus secondary butyl alcohol: A potential system for the exploration of a quadruple critical point

We report preliminary experiments on the ternary-liquid mixture, methyl ethyl ketone (MEK)+water (W)+secondary butyl alcohol (sBA)-a promising system for the realization of the quadruple critical point (QCP). The unusual tunnel-shaped phase diagram shown by this system is characterized and visualized by us in the form of a prismatic phase diagram. Light-scattering experiments reveal that (MEK+W+sBA) shows near three-dimensional-Ising type of critical behavior near the lower critical solution temperatures, with the susceptibility exponent (gamma) in the range of 1.217 <=gamma <= 1.246. The correlation length amplitudes (xi(o)) and the critical exponent (nu) of the correlation length (xi) are in the ranges of 3.536 <=xi(o)<= 4.611 A and 0.619 <=nu <= 0.633, respectively. An analysis in terms of the effective susceptibility exponent (gamma(eff)) shows that the critical behavior is of the Ising type for MEK concentrations in the ranges of 0.1000 <= X <= 0.1250 and X >= 0.3000. But, for the intermediate range of 0.1750 <= X < 0.3000, the system shows a tendency towards mean-field type of critical behavior. The advantages of the system (MEK+W+sBA) over the system (3-methylpyridine+water+heavy water+potassium Iodide) for the realization of a QCP are outlined.

A System-C based Micro architectural Exploration Framework for Latency, Power and Performance Trade-offs of On-Chip Interconnection

We describe a System-C based framework we are developing, to explore the impact of various architectural and microarchitectural level parameters of the on-chip interconnection network elements on its power and performance. The framework enables one to choose from a variety of architectural options like topology, routing policy, etc., as well as allows experimentation with various microarchitectural options for the individual links like length, wire width, pitch, pipelining, supply voltage and frequency. The framework also supports a flexible traffic generation and communication model. We provide preliminary results of using this framework to study the power, latency and throughput of a 4x4 multi-core processing array using mesh, torus and folded torus, for two different communication patterns of dense and sparse linear algebra. The traffic consists of both Request-Response messages (mimicing cache accesses)and One-Way messages. We find that the average latency can be reduced by increasing the pipeline depth, as it enables higher link frequencies. We also find that there exists an optimum degree of pipelining which minimizes energy-delay product.

Memory Architecture Exploration Framework for Cache Based Embedded SoC

Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and lower energy consumption. The memory architecture of the embedded system strongly influences critical system design objectives like area, power and performance. Hence the embedded system designer performs a complete memory architecture exploration to custom design a memory architecture for a given set of applications. Further, the designer would be interested in multiple optimal design points to address various market segments. However, tight time-to-market constraints enforces short design cycle time. In this paper we address the multi-level multi-objective memory architecture exploration problem through a combination of exhaustive-search based memory exploration at the outer level and a two step based integrated data layout for SPRAM-Cache based architectures at the inner level. We present a two step integrated approach for data layout for SPRAM-Cache based hybrid architectures with the first step as data-partitioning that partitions data between SPRAM and Cache, and the second step is the cache conscious data layout. We formulate the cache-conscious data layout as a graph partitioning problem and show that our approach gives up to 34% improvement over an existing approach and also optimizes the off-chip memory address space. We experimented our approach with 3 embedded multimedia applications and our approach explores several hundred memory configurations for each application, yielding several optimal design points in a few hours of computation on a standard desktop.

Design enhancement of the underwater noise control linings through a parsimonious parametric study

Control of sound transmission through the structure and reflection from the structure immersed in fluid media impose highly conflicting requirements on the design of the carpeted noise control linings. These requirements become even more stringent if the structure is expected to be moving with considerable speed particularly under intense hydrostatic pressure. Numerous configurations are possible for designing these linings. Therefore, in this paper, a few lining configurations are identified from the literature for parametric study so that the designer is provided with an environment to analyze and design the lining. A scheme of finite element analysis is used to analyze these linings for their acoustic performance. Commercial finite element software, NISA®, is used as a platform to develop a customized environment wherein design parameters of different configurations can be varied with consistency checks and generate the finite element meshes using the 8-noded hexahedral element. Four types of designs proposed and analysed here address the parameters of interest such as the echo reduction and the transmission loss. Study of the effect of different surface distributions of the cavities is carried out. Effect of static pressure on different designs is reported.

Streaming FFT on REDEFINE-v2: An Application-Architecture Design Space Exploration

In this paper we explore an implementation of a high-throughput, streaming application on REDEFINE-v2, which is an enhancement of REDEFINE. REDEFINE is a polymorphic ASIC combining the flexibility of a programmable solution with the execution speed of an ASIC. In REDEFINE Compute Elements are arranged in an 8x8 grid connected via a Network on Chip (NoC) called RECONNECT, to realize the various macrofunctional blocks of an equivalent ASIC. For a 1024-FFT we carry out an application-architecture design space exploration by examining the various characterizations of Compute Elements in terms of the size of the instruction store. We further study the impact by using application specific, vectorized FUs. By setting up different partitions of the FFT algorithm for persistent execution on REDEFINE-v2, we derive the benefits of setting up pipelined execution for higher performance. The impact of the REDEFINE-v2 micro-architecture for any arbitrary N-point FFT (N > 4096) FFT is also analyzed. We report the various algorithm-architecture tradeoffs in terms of area and execution speed with that of an ASIC implementation. In addition we compare the performance gain with respect to a GPP.

MODLEX: A Multi Objective Data Layout EXploration Framework for Embedded Systems-on-Chip

The memory subsystem is a major contributor to the performance, power, and area of complex SoCs used in feature rich multimedia products. Hence, memory architecture of the embedded DSP is complex and usually custom designed with multiple banks of single-ported or dual ported on-chip scratch pad memory and multiple banks of off-chip memory. Building software for such large complex memories with many of the software components as individually optimized software IPs is a big challenge. In order to obtain good performance and a reduction in memory stalls, the data buffers of the application need to be placed carefully in different types of memory. In this paper we present a unified framework (MODLEX) that combines different data layout optimizations to address the complex DSP memory architectures. Our method models the data layout problem as multi-objective genetic algorithm (GA) with performance and power being the objectives and presents a set of solution points which is attractive from a platform design viewpoint. While most of the work in the literature assumes that performance and power are non-conflicting objectives, our work demonstrates that there is significant trade-off (up to 70%) that is possible between power and performance.

MAX: A Multi Objective Memory Architecture eXploration Framework for Embedded Systems-on-Chip

Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and lower energy consumption. The memory architecture of the embedded system strongly influences these parameters. Hence the embedded system designer performs a complete memory architecture exploration. This problem is a multi-objective optimization problem and can be tackled as a two-level optimization problem. The outer level explores various memory architecture while the inner level explores placement of data sections (data layout problem) to minimize memory stalls. Further, the designer would be interested in multiple optimal design points to address various market segments. However, tight time-to-market constraints enforces short design cycle time. In this paper we address the multi-level multi-objective memory architecture exploration problem through a combination of Multi-objective Genetic Algorithm (Memory Architecture exploration) and an efficient heuristic data placement algorithm. At the outer level the memory architecture exploration is done by picking memory modules directly from a ASIC memory Library. This helps in performing the memory architecture exploration in a integrated framework, where the memory allocation, memory exploration and data layout works in a tightly coupled way to yield optimal design points with respect to area, power and performance. We experimented our approach for 3 embedded applications and our approach explores several thousand memory architecture for each application, yielding a few hundred optimal design points in a few hours of computation time on a standard desktop.

Design space exploration of systolic realization of QR factorization on a runtime reconfigurable platform

In the world of high performance computing huge efforts have been put to accelerate Numerical Linear Algebra (NLA) kernels like QR Decomposition (QRD) with the added advantage of reconfigurability and scalability. While popular custom hardware solution in form of systolic arrays can deliver high performance, they are not scalable, and hence not commercially viable. In this paper, we show how systolic solutions of QRD can be realized efficiently on REDEFINE, a scalable runtime reconfigurable hardware platform. We propose various enhancements to REDEFINE to meet the custom need of accelerating NLA kernels. We further do the design space exploration of the proposed solution for any arbitrary application of size n × n. We determine the right size of the sub-array in accordance with the optimal pipeline depth of the core execution units and the number of such units to be used per sub-array.

Performance modeling and architecture exploration of network processors

This paper proposes a Petri net model for a commercial network processor (Intel iXP architecture) which is a multithreaded multiprocessor architecture. We consider and model three different applications viz., IPv4 forwarding, network address translation, and IP security running on IXP 2400/2850. A salient feature of the Petri net model is its ability to model the application, architecture and their interaction in great detail. The model is validated using the Intel proprietary tool (SDK 3.51 for IXP architecture) over a range of configurations. We conduct a detailed performance evaluation, identify the bottleneck resource, and propose a few architectural extensions and evaluate them in detail.