7 resultados para Systolic Dysfunction

em Indian Institute of Science - Bangalore - Índia


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The paper presents two new algorithms for the direct parallel solution of systems of linear equations. The algorithms employ a novel recursive doubling technique to obtain solutions to an nth-order system in n steps with no more than 2n(n −1) processors. Comparing their performance with the Gaussian elimination algorithm (GE), we show that they are almost 100% faster than the latter. This speedup is achieved by dispensing with all the computation involved in the back-substitution phase of GE. It is also shown that the new algorithms exhibit error characteristics which are superior to GE. An n(n + 1) systolic array structure is proposed for the implementation of the new algorithms. We show that complete solutions can be obtained, through these single-phase solution methods, in 5n−log2n−4 computational steps, without the need for intermediate I/O operations.

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High-speed evaluation of a large number of linear, quadratic, and cubic expressions is very important for the modeling and real-time display of objects in computer graphics. Using VLSI techniques, chips called pixel planes have actually been built by H. Fuchs and his group to evaluate linear expressions. In this paper, we describe a topological variant of Fuchs' pixel planes which can evaluate linear, quadratic, cubic, and higher-order polynomials. In our design, we make use of local interconnections only, i.e., interconnections between neighboring processing cells. This leads to the concept of tiling the processing cells for VLSI implementation.

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In this paper, we propose a systolic architecture for hidden-surface removal. Systolic architecture is a kind of parallel architecture best known for its easy VLSI implementability. After discussing the design details of the architecture, we present the results of the simulation experiments conducted in order to evaluate the performance of the architecture.

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With the advent of VLSI it has become possible to map parallel algorithms for compute-bound problems directly on silicon. Systolic architecture is very good candidate for VLSI implementation because of its regular and simple design, and regular communication pattern. In this paper, a systolic algorithm and corresponding systolic architecture, a linear systolic array, for the scanline-based hidden surface removal problem in three-dimensional computer graphics have been proposed. The algorithm is based on the concept of sample spans or intervals. The worst case time taken by the algorithm is O(n), n being the number of segments in a scanline. The time taken by the algorithm for a given scene depends on the scene itself, and on an average considerable improvement over the worst case behaviour is expected. A pipeline scheme for handling the I/O process has also been proposed which is suitable for VLSI implementation of the algorithm.

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In the world of high performance computing huge efforts have been put to accelerate Numerical Linear Algebra (NLA) kernels like QR Decomposition (QRD) with the added advantage of reconfigurability and scalability. While popular custom hardware solution in form of systolic arrays can deliver high performance, they are not scalable, and hence not commercially viable. In this paper, we show how systolic solutions of QRD can be realized efficiently on REDEFINE, a scalable runtime reconfigurable hardware platform. We propose various enhancements to REDEFINE to meet the custom need of accelerating NLA kernels. We further do the design space exploration of the proposed solution for any arbitrary application of size n × n. We determine the right size of the sub-array in accordance with the optimal pipeline depth of the core execution units and the number of such units to be used per sub-array.

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Parkinsons disease (PD) is the second most prevalent progressive neurological disorder commonly associated with impaired mitochondrial function in dopaminergic neurons. Although familial PD is multifactorial in nature, a recent genetic screen involving PD patients identified two mitochondrial Hsp70 variants (P509S and R126W) that are suggested in PD pathogenesis. However, molecular mechanisms underlying how mtHsp70 PD variants are centrally involved in PD progression is totally elusive. In this article, we provide mechanistic insights into the mitochondrial dysfunction associated with human mtHsp70 PD variants. Biochemically, the R126W variant showed severely compromised protein stability and was found highly susceptible to aggregation at physiological conditions. Strikingly, on the other hand, the P509S variant exhibits significantly enhanced interaction with J-protein cochaperones involved in folding and import machinery, thus altering the overall regulation of chaperone-mediated folding cycle and protein homeostasis. To assess the impact of mtHsp70 PD mutations at the cellular level, we developed yeast as a model system by making analogous mutations in Ssc1 ortholog. Interestingly, PD mutations in yeast (R103W and P486S) exhibit multiple in vivo phenotypes, which are associated with omitochondrial dysfunction', including compromised growth, impairment in protein translocation, reduced functional mitochondrial mass, mitochondrial DNA loss, respiratory incompetency and increased susceptibility to oxidative stress. In addition to that, R103W protein is prone to aggregate in vivo due to reduced stability, whereas P486S showed enhanced interaction with J-proteins, thus remarkably recapitulating the cellular defects that are observed in human PD variants. Taken together, our findings provide evidence in favor of direct involvement of mtHsp70 as a susceptibility factor in PD.