Within-Die Gate Delay Variability Measurement Using Reconfigurable Ring Oscillator

We report the design and characterization of a circuit technique to measure the on-chip delay of an individual logic gate (both inverting and noninverting) in its unmodified form. The test circuit comprises of digitally reconfigurable ring oscillator (RO). The gate under test is embedded in each stage of the ring oscillator. A system of linear equations is then formed with different configuration settings of the RO, relating the individual gate delay to the measured period of the RO, whose solution gives the delay of the individual gates. Experimental results from a test chip in 65-nm process node show the feasibility of measuring the delay of an individual inverter to within 1 ps accuracy. Delay measurements of different nominally identicall inverters in close physical proximity show variations of up to 28% indicating the large impact of local variations. As a demonstration of this technique, we have studied delay variation with poly-pitch, length of diffusion (LOD) and different orientations of layout in silicon. The proposed technique is quite suitable for early process characterization, monitoring mature process in manufacturing and correlating model-to-hardware.

Minimizing total weighted tardiness on a batch-processing machine with non-agreeable release times and due dates

This study considers the scheduling problem observed in the burn-in operation of semiconductor final testing, where jobs are associated with release times, due dates, processing times, sizes, and non-agreeable release times and due dates. The burn-in oven is modeled as a batch-processing machine which can process a batch of several jobs as long as the total sizes of the jobs do not exceed the machine capacity and the processing time of a batch is equal to the longest time among all the jobs in the batch. Due to the importance of on-time delivery in semiconductor manufacturing, the objective measure of this problem is to minimize total weighted tardiness. We have formulated the scheduling problem into an integer linear programming model and empirically show its computational intractability. Due to the computational intractability, we propose a few simple greedy heuristic algorithms and meta-heuristic algorithm, simulated annealing (SA). A series of computational experiments are conducted to evaluate the performance of the proposed heuristic algorithms in comparison with exact solution on various small-size problem instances and in comparison with estimated optimal solution on various real-life large size problem instances. The computational results show that the SA algorithm, with initial solution obtained using our own proposed greedy heuristic algorithm, consistently finds a robust solution in a reasonable amount of computation time.

Scheduling parallel batch processors with incompatible job families using ant colony optimization

The present work concerns with the static scheduling of jobs to parallel identical batch processors with incompatible job families for minimizing the total weighted tardiness. This scheduling problem is applicable in burn-in operations and wafer fabrication in semiconductor manufacturing. We decompose the problem into two stages: batch formation and batch scheduling, as in the literature. The Ant Colony Optimization (ACO) based algorithm called ATC-BACO algorithm is developed in which ACO is used to solve the batch scheduling problems. Our computational experimentation shows that the proposed ATC-BACO algorithm performs better than the available best traditional dispatching rule called ATC-BATC rule.

A novel laser direct write technique for fabrication of thin film MICs

A technique for fabrication of thin-film circuits for microwave integrated circuit (MIC) application is presented. This low-cost fabrication technique utilizes laser direct write of copper patterns on alumina substrates. The method obviates the need for photomasks and photolithography. The film deposition mechanism, deposit film analysis, and MIC fabrication sequence are presented. Performance evaluation of MICs fabricated using this technique is also included

Minimizing total completion time on batch processing machines

We study the problem of minimizing total completion time on single and parallel batch processing machines. A batch processing machine is one which can process up to B jobs simultaneously. The processing time of a batch is equal to the largest processing time among all jobs in the batch. This problem is motivated by burn-in operations in the final testing stage of semiconductor manufacturing and is expected to occur in other production environments. We provide an exact solution procedure for the single-machine problem and heuristic algorithms for both single and parallel machine problems. While the exact algorithms have limited applicability due to high computational requirements, extensive experiments show that the heuristics are capable of consistently obtaining near-optimal solutions in very reasonable CPU times.

Voltage and Temperature-Aware SSTA Using Neural Network Delay Model

With the emergence of voltage scaling as one of the most powerful power reduction techniques, it has been important to support voltage scalable statistical static timing analysis (SSTA) in deep submicrometer process nodes. In this paper, we propose a single delay model of logic gate using neural network which comprehensively captures process, voltage, and temperature variation along with input slew and output load. The number of simulation programs with integrated circuit emphasis (SPICE) required to create this model over a large voltage and temperature range is found to be modest and 4x less than that required for a conventional table-based approach with comparable accuracy. We show how the model can be used to derive sensitivities required for linear SSTA for an arbitrary voltage and temperature. Our experimentation on ISCAS 85 benchmarks across a voltage range of 0.9-1.1V shows that the average error in mean delay is less than 1.08% and average error in standard deviation is less than 2.85%. The errors in predicting the 99% and 1% probability point are 1.31% and 1%, respectively, with respect to SPICE. The two potential applications of voltage-aware SSTA have been presented, i.e., one for improving the accuracy of timing analysis by considering instance-specific voltage drops in power grids and the other for determining optimum supply voltage for target yield for dynamic voltage scaling applications.

Photoresist functionalisation method for high-density protein microarrays using photolithography

Since the last decade, there is a growing need for patterned biomolecules for various applications ranging from diagnostic devices to enabling fundamental biological studies with high throughput. Protein arrays facilitate the study of protein-protein, protein-drug or protein-DNA interactions as well as highly multiplexed immunosensors based on antibody-antigen recognition. Protein microarrays are typically fabricated using piezoelectric inkjet printing with resolution limit of similar to 70-100 mu m limiting the array density. A considerable amount of research has been done on patterning biomolecules using customised biocompatible photoresists. Here, a simple photolithographic process for fabricating protein microarrays on a commercially available diazo-naphthoquinone-novolac-positive tone photoresist functionalised with 3-aminopropyltriethoxysilane is presented. The authors demonstrate that proteins immobilised using this procedure retain their activity and therefore form functional microarrays with the array density limited only by the resolution of lithography, which is more than an order of magnitude compared with inkjet printing. The process described here may be useful in the integration of conventional semiconductor manufacturing processes with biomaterials relevant for the creation of next-generation bio-chips.

Effect of Process Deviations on Performance of Piezoresistive Pressure Sensors

Diaphragm thickness and the corresponding piezoresistor locations change due to over or under etching in bulk micromachined piezoresistive pressure sensor which intern influences the device performance. In the present work, variation of sensitivity and nonlinearity of a micro electro mechanical system low pressure sensor is investigated. The sensor is modeled using finite element method to analyze the variation of sensitivity and nonlinearity with diaphragm thickness. To verify the simulated results, the sensors with different diaphragm thicknesses are fabricated. The models are verified by comparing the calculated results with experimental data. This study is potentially useful for the researchers as most of the times the diaphragm is either over-etched or under-etched due to inherent variation in wafer thickness and involving manual operations.

Structural and optical investigation of semiconductor CdSe/CdS core-shell quantum dot thin films

Highly luminescent CdSe/CdS core-shell nanocrystals have been assembled on indium tin oxide (ITO) coated glass substrates using a wet synthesis route. The physical properties of the quantum dots (QD) have been investigated using X-ray diffraction, transmission electron microscopy and optical absorption spectroscopy techniques. These quantum dots showed a strong enhancement in the near band edge absorption. The in situ luminescence behavior has been interpreted in the light of the quantum confinement effect and induced strain in the core-shell structure.

The dynamics of polymerized carbon nanotubes in semiconductor polymer electronics and electro-mechanical sensing

Polymerized carbon nanotubes (CNTs) are promising materials for polymer-based electronics and electro-mechanical sensors. The advantage of having a polymer nanolayer on CNTs widens the scope for functionalizing it in various ways for polymer electronic devices. However, in this paper, we show for the first time experimentally that, due to a resistive polymer layer having carbon nanoparticle inclusions and polymerized carbon nanotubes, an interesting dynamics can be exploited. We first show analytically that the relative change in the resistance of a single isolated semiconductive nanotube is directly proportional to the axial and torsional dynamic strains, when the strains are small, whereas, in polymerized CNTs, the viscoelasticity of the polymer and its effective electrical polarization give rise to nonlinear effects as a function of frequency and bias voltage. A simplified formula is derived to account for these effects and validated in the light of experimental results. CNT–polymer-based channels have been fabricated on a PZT substrate. Strain sensing performance of such a one-dimensional channel structure is reported. For a single frequency modulated sine pulse as input, which is common in elastic and acoustic wave-based diagnostics, imaging, microwave devices, energy harvesting, etc, the performance of the fabricated channel has been found to be promising.

Electrical and mechanical properties of diluted magnetic semiconductor Zn1-xMnxS nanocrystalline films

Nanostructured Zn1-xMnxS films (0 less-than-or-equals, slant x less-than-or-equals, slant 0.25) were deposited on glass substrates by simple resistive thermal evaporation technique. All the films were deposited at 300 K in a vacuum of 2*10-6 m bar. All the films temperature dependence of resistivity revealed semiconducting behaviour of the samples. Hot probe test revealed that all the samples exhibited n-type conductivity. The nanohardness of the films ranges from 4.7 to 9.9 GPa, Young's modulus value ranging 69.7-94.2 GPa.

Temperature measurements in the boron carbide manufacturing process - A hot model study

Boron carbide is produced in a heat resistance furnace using boric oxide and petroleum coke as the raw materials. The product yield is very low. Heat transfer plays an important role in the formation of boron carbide. Temperature at the core reaches up to 2600 K. No experimental study is available in the open literature for this high temperature process particularly in terms of temperature measurement and heat transfer. Therefore, a laboratory scale hot model of the process has been setup to measure the temperatures in harsh conditions at different locations in the furnace using various temperature measurement devices such as pyrometer and various types of thermocouple. Particular attention was paid towards the accuracy and reliability of the measured data. The recorded data were analysed to understand the heat transfer process inside the reactor and the effect of it on the formation of boron carbide.

Doping Dependence of Semiconductor-Metal Transition in InP at High Pressures

The resistivity of selenium-doped n-InP single crystal layers grown by liquid-phase epitaxy with electron concentrations varying from 6.7 x 10$^18$ to 1.8 x 10$^20$ cm$^{-3}$ has been measured as a function of hydrostatic pressure up to 10 GPa. Semiconductor-metal transitions were observed in each case with a change in resistivity by two to three orders of magnitude. The transition pressure p$_c$ decreased monotonically from 7.24 to 5.90 GPa with increasing doping concentration n according to the relation $p_c = p_o [1 - k(n/n_m)^a]$, where n$_m$ is the concentration (per cubic centimetre) of phosphorus donor sites in InP atoms, p$_o$ is the transition pressure at low doping concentrations, k is a constant and $\alpha$ is an exponent found experimentally to be 0.637. The decrease in p$_c$ is considered to be due to increasing internal stress developed at high concentrations of ionized donors. The high-pressure metallic phase had a resistivity (2.02-6.47) x 10$^{-7}$ $\Omega$ cm, with a positive temperature coefficient dependent on doping.