A DLTS technique for surface state capture cross-section measurement of MOS diodes

A modified DLTS technique is proposed for the direct measurement of capture cross-section of MOS surface states. The nature of temperature and energy dependence σn is inferred from data analysis. Temperature dependence of σn is shown to be consistent with the observed DLTS line shapes.

Interface states of laser ablated BaTiO3 and Ba0.9Ca0.1TiO3 thin films in MFS structure determined by DLTS and C – V technique

BaTiO3 and Ba0.9Ca0.1TiO3 thin films were deposited on the p – type Si substrate by pulsed excimer laser ablation technique. The Capacitance – Voltage (C-V) measurement measured at 1 MHz exhibited a clockwise rotating hysteresis loop with a wide memory window for the Metal – Ferroelectric – Semiconductor (MFS) capacitor confirming the ferroelectric nature. The low frequency C – V measurements exhibited the response of the minority carriers in the inversion region while at 1 MHz the C – V is of a high frequency type with minimum capacitance in the inversion region. The interface states of both the MFS structures were calculated from the Castagne – Vaipaille method (High – low frequency C – V curve). Deep Level Transient Spectroscopy (DLTS) was used to analyze the interface traps and capture cross section present in the MFS capacitor. There were distinct peaks present in the DLTS spectrum and these peaks were attributed to the presence of the discrete interface states present at the semiconductor – ferroelectric interface. The distribution of calculated interface states were mapped with the silicon energy band gap for both the undoped and Ca doped BaTiO3 thin films using both the C – V and DLTS method. The interface states of the Ca doped BaTiO3 thin films were found to be higher than the pure BaTiO3 thin films.

DLTS analysis of amphoteric interface defects in high-TiO2 MOS structures prepared by sol-gel spin-coating

High-kappa TiO2 thin films have been fabricated from a facile, combined sol-gel spin - coating technique on p and n type silicon substrate. XRD and Raman studies headed the existence of anatase phase of TiO2 with a small grain size of 18 nm. The refractive index `n' quantified from ellipsometry is 2.41. AFM studies suggest a high quality, pore free films with a fairly small surface roughness of 6 angstrom. The presence of Ti in its tetravalent state is confirmed by XPS analysis. The defect parameters observed at the interface of Si/TiO2 were studied by capacitance - voltage (C - V) and deep level transient spectroscopy (DLTS). The flat - band voltage (V-FB) and the density of slow interface states estimated are -0.9, -0.44 V and 5.24x10(10), 1.03x10(11) cm(-2); for the NMOS and PMOS capacitors, respectively. The activation energies, interface state densities and capture cross -sections measured by DLTS are E-V + 0.30, E-C - 0.21 eV; 8.73x10(11), 6.41x10(11) eV(-1) cm(-2) and 5.8x10(-23), 8.11x10(-23) cm(2) for the NMOS and PMOS structures, respectively. A low value of interface state density in both P-and N-MOS structures makes it a suitable alternate dielectric layer for CMOS applications. And also very low value of capture cross section for both the carriers due to the amphoteric nature of defect indicates that the traps are not aggressive recombination centers and possibly can not contribute to the device operation to a large extent. (C) 2015 Author(s).

A simple circuit to aid direct measurement of capture cross sections of deep level impurities

An inexpensive and simple circuit to aid the direct measurement of majority carrier capture cross sections of impurity levels in the band gap of a semiconductor by the variable width filling pulse technique is presented. With proper synchronisation, during the period of application of the pulse, the device is disconnected from the capacitance meter to avoid distortion of the pulse and is reconnected again to the meter to record the emission transient. Modes of operation include manual triggering for long emission transients, repetitive triggering for isothermal and DLTS measurements and the DLTS mode which is to be used with signal analysers that already provide a synchronising pulse for disconnection.

Properties of iron related quenched-in levels in p-silicon

The electrical and optical properties of the thermally induced quenched-in levels in p-silicon which have heen attributed to iron are studied. The two levels, HI and H2, are located at Ev + 0.42 eV and Ev + 0.52 eV, respectively, as determined by TSCAP, DLTS, and transient photocapacitance methods. The photoionization cross sections are well described by Lucovsky's model. The hole capture by H1 is temperature dependent; a barrier of 40 meV is measured. However, multiphonon emission mechanism cannot be invoked to explain this temperature dependence due to the inferred zero lattice relaxation. The source of iron contamination is found to be the ambient conditions, in particular the quartz tube. The conflicting reports regarding the stability and the variation in the reported capture cross section values suggests that the observed Ev + 0.4 eV level must be a complex centre. The inferred near zero lattice relaxation during the electron transition implies weak coupling to the host lattice.

Investigation of Deep Defects Due to -Particle Irradiation in n-Silicon

Electrical properties of deep defects induced in n-silicon by -particles of about 10 MeV energy at a dose of 1014 and 1015 cm-2 are studied by DLTS. The levels at Ec -0.18 eV, Ec -0.26 eV, and Ec -0.48 eV are identified as A center, V2 (=/-) and V2 (-/0) on the basis of activation energy, electron capture cross section, and annealing behavior. Two other irradiation related levels at Ec -0.28 eV and Ec -0.51 eV could not be related to any known center.

Properties of the gold related acceptor level in silicon

The apparent thermal activation energy of 0.56 eV and the electron thermal capture cross section of 2.0 × 10-16 cm2 are measured for the gold related acceptor level in p+ nn+ silicon diodes by isothermal current transient and DLTS techniques. Using the emission and capture rate data and a degeneracy ratio of 2, the energy separation of the trap level from the conduction band is calculated and found to have the same temperature dependence as the band gap indicating that the acceptor level is pinned with respect to the valence band a t Ev + 0.637 eV.

System effects in double‐channel gated‐integrator‐based deep‐level transient spectroscopy

The effects of the two sampling gate positions, and their widths and the integrator response times on the position, height, and shape of the peaks obtained in a double‐channel gated‐integrator‐based deep‐level transient spectroscopy (DLTS) system are evaluated. The best compromise between the sensitivity and the resolution of the DLTS system is shown to be obtained when the ratio of the two sampling gate positions is about 20. An integrator response time of about 100 ms is shown to be suitable for practical values of emission time constants and heating rates generally used.

Studies on process induced deep levels in silicon

An attempt was made to study the deep level impurities and defects introduced into thyristor grade silicon under different processing conditions. DLTS, C-V and I-V measurements were carried out. The ideality factors of the diodes is around 1-7. Activation energy, trap density and minority carrier lifetime were measured.

A deep‐level spectroscopic technique for determining capture cross‐section activation energy of Si‐related DX centers in AlxGa1-xAs

A deep‐level transient spectroscopy (DLTS) technique is reported for determining the capture cross‐section activation energy directly. Conventionally, the capture activation energy is obtained from the temperature dependence of the capture cross section. Capture cross‐section measurement is often very doubtful due to many intrinsic errors and is more critical for nonexponential capture kinetics. The essence of this technique is to use an emission pulse to allow the defects to emit electrons and the transient signal from capture process due to a large capture barrier was analyzed, in contrast with the emission signal in conventional DLTS. This technique has been applied for determining the capture barrier for silicon‐related DX centers in AlxGa1−xAs for different AlAs mole fractions.