Polypyrrole based amperometric glucose biosensors

Biosensors have gained immense acceptance in the field of medical diagnostics, besides environmental, food safety and biodefence applications due to its attributes of real-time and rapid response. This synergistic combination of biotechnology and microelectronics comprises a biological recognition element coupled with a compatible transducer device. Diabetes is a disease of major concern since the ratio of world population suffering from it is increasing at an alarming rate and therefore the need for development of accurate and stable glucose biosensors is evident. There are many commercial glucose biosensors available yet some limitations need attention. This review presents a detailed account of the polypyrrole based amperometric glucose biosensors. The polymer polypyrrole is used extensively as a matrix for immobilization of glucose oxidase enzyme owing to its favourable features such as stability under ambient conditions, conductivity that allows it to be used as an electron relay, ability to be polymerized under neutral and aqueous mild conditions, and more. The simple one-step electrodeposition on the electrode surface allows easy entrapment of the enzyme. The review is structured into three categories (a) the first-stage biosensors: which report the studies from the inception of use of polypyrrole in glucose biosensors during which time the role of the polymer and the use of mediators was established. This period saw extensive work by two separate groups of Schuhmann and Koopal who contributed a great deal in understanding the electron transfer pathways in polypyrrole based glucose biosensors, (b) the second-stage biosensors: which highlight the shift of polypyrrole from a conventional matrix to composite matrices with extensive use of mediators focused at improving the selectivity of response, and (c) third-stage biosensors: the remarkable properties of nanoparticles and carbon nanotubes and their outstanding ability to mediate electrontransfers have seen their indispensable use in conjugation with polypyrrole for development of glucose biosensors with improved sensitivity and stability characteristics which is accounted in the review, which thus traces the evolution of polypyrrole from a conventional matrix, to composites and thence to the form of nanotube arrays, with the objective of addressing the vital issue of diabetes management through the development of stable and reliable glucose biosensors.

Drive current boosting of n-type tunnel FET with strained SiGe layer at source

Though silicon tunnel field effect transistor (TFET) has attracted attention for sub-60 mV/decade subthreshold swing and very small OFF current (IOFF), its practical application is questionable due to low ON current (ION) and complicated fabrication process steps. In this paper, a new n-type classical-MOSFET-alike tunnel FET architecture is proposed, which offers sub-60 mV/decade subthreshold swing along with a significant improvement in ION. The enhancement in ION is achieved by introducing a thin strained SiGe layer on top of the silicon source. Through 2D simulations it is observed that the device is nearly free from short channel effect (SCE) and its immunity towards drain induced barrier lowering (DIBL) increases with increasing germanium mole fraction. It is also found that the body bias does not change the drive current but after body current gets affected. An ION of View the MathML source and a minimum average subthreshold swing of 13 mV/decade is achieved for 100 nm channel length device with 1.2 V supply voltage and 0.7 Ge mole fraction, while maintaining the IOFF in fA range.

Studies on design, fabrication and reliability assessment of embedded passives on a high-density interconnect (HDI) organic substrate using a sequential build-up process

One of the foremost design considerations in microelectronics miniaturization is the use of embedded passives which provide practical solution. In a typical circuit, over 80 percent of the electronic components are passives such as resistors, inductors, and capacitors that could take up to almost 50 percent of the entire printed circuit board area. By integrating passive components within the substrate instead of being on the surface, embedded passives reduce the system real estate, eliminate the need for discrete and assembly, enhance electrical performance and reliability, and potentially reduce the overall cost. Moreover, it is lead free. Even with these advantages, embedded passive technology is at a relatively immature stage and more characterization and optimization are needed for practical applications leading to its commercialization.This paper presents an entire process from design and fabrication to electrical characterization and reliability test of embedded passives on multilayered microvia organic substrate. Two test vehicles focusing on resistors and capacitors have been designed and fabricated. Embedded capacitors in this study are made with polymer/ceramic nanocomposite (BaTiO3) material to take advantage of low processing temperature of polymers and relatively high dielectric constant of ceramics and the values of these capacitors range from 50 pF to 1.5 nF with capacitance per area of approximately 1.5 nF/cm(2). Limited high frequency measurement of these capacitors was performed. Furthermore, reliability assessments of thermal shock and temperature humidity tests based on JEDEC standards were carried out. Resistors used in this work have been of three types: 1) carbon ink based polymer thick film (PTF), 2) resistor foils with known sheet resistivities which are laminated to printed wiring board (PWB) during a sequential build-up (SBU) process and 3) thin-film resistor plating by electroless method. Realization of embedded resistors on conventional board-level high-loss epoxy (similar to 0.015 at 1 GHz) and proposed low-loss BCB dielectric (similar to 0.0008 at > 40 GHz) has been explored in this study. Ni-P and Ni-W-P alloys were plated using conventional electroless plating, and NiCr and NiCrAlSi foils were used for the foil transfer process. For the first time, Benzocyclobutene (BCB) has been proposed as a board level dielectric for advanced System-on-Package (SOP) module primarily due to its attractive low-loss (for RF application) and thin film (for high density wiring) properties.Although embedded passives are more reliable by eliminating solder joint interconnects, they also introduce other concerns such as cracks, delamination and component instability. More layers may be needed to accommodate the embedded passives, and various materials within the substrate may cause significant thermo -mechanical stress due to coefficient of thermal expansion (CTE) mismatch. In this work, numerical models of embedded capacitors have been developed to qualitatively examine the effects of process conditions and electrical performance due to thermo-mechanical deformations.Also, a prototype working product with the board level design including features of embedded resistors and capacitors are underway. Preliminary results of these are presented.

Si, Si-Ge and the new heterostructure world

Semiconductor heterostructures based on AlAs/GaAs and other III-V compounds have been the focus of active research for some time now. Ih the last decade, a new heterostructure material, the strained Si/SiGe system, has emerged. This heterojunction technology can potentially be integrated into the current VLSI environment with large-scale impact in the growing microelectronics market. Si/SiGe heterojunction bipolar transistors with cut-off frequencies exceeding 100 GHz and other electronic and optical devices with superior properties compared to all-Si technology have been demonstrated in laboratories worldwide.

Overview of neurocomputers

This paper presents an introduction to neurocomputers and an overview of the history of neurocomputers. Direct implementation methods of neurocomputers using techniques from microelectronics and photonics are discussed. Emulation methods using special-purpose hardware are highlighted. The role of parallel computing systems for improved performance is introduced. Some commercially available neurocomputers and performance issues of such systems are also presented.

Photo-Defined Electrically Assisted Etching Method for Metal Stencil Fabrication

Metal stencils are well known in electronics printing application such as for dispensing solder paste for surface mounting, printing embedded passive elements in multilayer structures, etc. For microprinting applications using stencils, the print quality depends on the smoothness of the stencil aperture and its dimensional accuracy, which in turn are invariably related to the method used to manufacture the stencils. In this paper, fabrication of metal stencils using a photo-defined electrically assisted etching method is described. Apertures in the stencil were made in neutral electrolyte using three different types of impressed current, namely, dc, pulsed dc, and periodic pulse reverse (PPR). Dimensional accuracy and wall smoothness of the etched apertures in each of the current waveforms were compared. Finally, paste transfer efficiency of the stencil obtained using PPR was calculated and compared with those of a laser-cut electropolished stencil. It is observed that the stencil fabricated using current in PPR waveform has better dimensional accuracy and aperture wall smoothness than those obtained with dc and pulsed dc. From the paste transfer efficiency experiment, it is concluded that photo-defined electrically assisted etching method can provide an alternate route for fabrication of metal stencils for future microelectronics printing applications.

Backward switching phenomenon from field forced ferroelectric to antiferroelectric phases in antiferroelectric PbZrO3 thin films

Antiferroelectric materials (example: lead zirconate and modified lead zirconate stannate), in which a field-induced ferroelectric phase transition is feasible due to a small free energy difference between the ferroelectric and the antiferroelectric phases, are proven to be very good candidates for applications involving actuation and high charge storage devices. The property of reverse switching from the field-induced ferroelectric to antiferroelectric phases is studied as a function of temperature, applied electric field, and sample thickness in antiferroelectric lead zirconate thin films deposited by pulsed excimer laser ablation. The maximum released charge density was 22 μC/cm2 from a stored charge density of 36 μC/cm2 in a 0.55 μ thick lead zirconate thin film. This indicated that more than 60% of the stored charge could be released in less than 7 ns at room temperature for a field of 200 kV/cm. The content of net released charge was found to increase with increasing field strength, whereas with increasing temperature the released charge was found to decrease. Thickness-dependent studies on lead zirconate thin films showed that size effects relating to extrinsic and intrinsic pinning mechanisms controlled the released and induced charges through the intrinsic switching time. These results proved that antiferroelectric PZ thin films could be utilized in high-speed charge decoupling capacitors in microelectronics applications.

Design of a Low Power 64 Point FFT Architecture for WLAN Applications

This paper presents a Radix-4(3) based FFT architecture suitable for OFDM based WLAN applications. The radix-4(3) parallel unrolled architecture presented here, uses a radix-4 butterfly unit which takes all four inputs in parallel and can selectively produce one out of the four outputs. A 64 point FFT processor based on the proposed architecture has been implemented in UMC 130nm 1P8M CMOS process with a maximum clock frequency of 100 MHz and area of 0.83mm(2). The proposed processor provides a throughput of four times the clock rate and can finish one 64 point FFT computation in 16 clock cycles. For IEEE 802.11a/g WLAN, the processor needs to be operated at a clock rate of 5 MHz with a power consumption of 2.27 mW which is 27% less than the previously reported low power implementations.

A zero charge-pump mismatch current tracking loop for reference spur reduction in PLLs

The charge-pump (CP) mismatch current is a dominant source of static phase error and reference spur in the nano-meter CMOS PLL implementations due to its worsened channel length modulation effect. This paper presents a charge-pump (CP) mismatch current reduction technique utilizing an adaptive body bias tuning of CP transistors and a zero CP mismatch current tracking PLL architecture for reference spur suppression. A chip prototype of the proposed circuit was implemented in 0.13 mu m CMOS technology. The frequency synthesizer consumes 8.2 mA current from a 13 V supply voltage and achieves a phase noise of -96.01 dBc/Hz @ 1 MHz offset from a 2.4 GHz RF carrier. The charge-pump measurements using the proposed calibration technique exhibited a mismatch current of less than 0.3 mu A (0.55%) over the VCO control voltage range of 0.3-1.0 V. The closed loop measurements show a minimized static phase error of within +/- 70 ps and a similar or equal to 9 dB reduction in reference spur level across the PLL output frequency range 2.4-2.5 GHz. The presented CP calibration technique compensates for the DC current mismatch and the mismatch due to channel length modulation effect and therefore improves the performance of CP-PLLs in nano-meter CMOS implementations. (C) 2015 Elsevier Ltd. All rights reserved.