Mesostructured lamellar chromium oxide

Mesostructured lamellar chromium oxide with an interlayer separation of 29 Angstrom has been prepared by employing a cationic surfactant. The introduction of phosphate groups in the oxide increases the interlayer separation to 32 Angstrom.

Preparation of lamellar and hexagonal forms of mesoporous silica and zirconiaby the neutral amine route: lamellar-hexagonal transformation in the solid state

The chain length of the surfactant and the solvent composition are two of the factors that determine whether the lamellar or the hexagonal form of mesoporous SiO2 (or ZrO2) is formed by the neutral amine route; a lamellar-hexagonal transformation occurs on removal of the amine from the former.

Multiscale modeling of lamellar mesophases

The mesoscale simulation of a lamellar mesophase based on a free energy functional is examined with the objective of determining the relationship between the parameters in the model and molecular parameters. Attention is restricted to a symmetric lamellar phase with equal volumes of hydrophilic and hydrophobic components. Apart from the lamellar spacing, there are two parameters in the free energy functional. One of the parameters, r, determines the sharpness of the interface, and it is shown how this parameter can be obtained from the interface profile in a molecular simulation. The other parameter, A, provides an energy scale. Analytical expressions are derived to relate these parameters to r and A to the bending and compression moduli and the permeation constant in the macroscopic equation to the Onsager coefficient in the concentration diffusion equation. The linear hydrodynamic response predicted by the theory is verified by carrying out a mesoscale simulation using the lattice-Boltzmann technique and verifying that the analytical predictions are in agreement with simulation results. A macroscale model based on the layer thickness field and the layer normal field is proposed, and the relationship between the parameters in the macroscale model from the parameters in the mesoscale free energy functional is obtained.

On-Chip Clock Network Skew Measurement using Sub-Sampling

We present a technique for an all-digital on-chip delay measurement system to measure the skews in a clock distribution network. It uses the principle of sub-sampling. Measurements from a prototype fabricated in a 65 nm industrial process, indicate the ability to measure delays with a resolution of 0.5ps and a DNL of 1.2 ps.

Mesoscale description of an asymmetric lamellar phase

The relationship between the parameters in a description based on a mesoscale free energy functional for the concentration field and the macroscopic properties, such as the bending and compression moduli and the permeation constant, are examined for an asymmetric lamellar phase where the mass fractions of the hydrophobic and hydrophilic parts are not equal. The difference in the mass fractions is incorporated using a cubic term in the free energy functional, in addition to the usual quadratic and quartic terms in the Landau–Ginsburg formulation. The relationship between the coefficient of the cubic term and the difference in the mass fractions of the hydrophilic and hydrophobic parts is obtained. For a lamellar phase, it is important to ensure that the surface tension is zero due to symmetry considerations. The relationship between the parameters in the free energy functional for zero surface tension is derived. When the interface between the hydrophilic and hydrophobic parts is diffuse, it is found that the bending and compression moduli, scaled by the parameters in the free energy functional, do increase as the asymmetry in the bilayer increases. When the interface between the hydrophilic and hydrophobic parts is sharp, the scaled bending and compression moduli show no dependence on the asymmetry in the bilayer. The ratio of the permeation constant in between the water and bilayer in a molecular description and the Onsager coefficient in the mesoscale description is O(1) for both sharp and diffuse interfaces and it increases as the difference in the mass fractions is increased.

Influence of tool rake angle on the quality of pure magnesium chip-consolidated product

Chips were produced by orthogonal Cutting of cast pure magnesium billet with three different tool rake angles viz., -15 degrees, -5 degrees and +15 degrees on a lathe. Chip consolidation by solid state recycling technique involved cold compaction followed by hot extrusion. The extruded products were characterized for microstructure and mechanical properties. Chip-consolidated products from -15 degrees rake angle tools showed 19% increase in tensile strength, 60% reduction ingrain size and 12% increase in hardness compared to +15 degrees rake chip-consolidated product indicating better chip bonding and grain refinement. Microstructure of the fracture specimen Supports the abovefinding. On the overall, the present work high lights the importance of tool take angle in determining the quality of the chip-consolidated products. (C) 2009 Elsevier B.V. All rights reserved.

Power Optimal Network-on-Chip Interconnect Design

A large part of today's multi-core chips is interconnect. Increasing communication complexity has made essential new strategies for interconnects, such as Network on Chip. Power dissipation in interconnects has become a substantial part of the total power dissipation. Techniques to reduce interconnect power have thus become a necessity. In this paper, we present a design methodology that gives values of bus width for interconnect links, frequency of operation for routers, in Network on Chip scenario that satisfy required throughput and dissipate minimal switching power. We develop closed form analytical expressions for the power dissipation, with bus width and frequency as variables and then use Lagrange multiplier method to arrive at the optimal values. We present a 4 port router in 90 nm technology library as case study. The results obtained from analysis are discussed.

Generic Routing Rules and a Scalable Access Enhancement for the Network-on-Chip RECONNECT

RECONNECT is a Network-on-Chip using a honeycomb topology. In this paper we focus on properties of general rules applicable to a variety of routing algorithms for the NoC which take into account the missing links of the honeycomb topology when compared to a mesh. We also extend the original proposal [5] and show a method to insert and extract data to and from the network. Access Routers at the boundary of the execution fabric establish connections to multiple periphery modules and create a torus to decrease the node distances. Our approach is scalable and ensures homogeneity among the compute elements in the NoC. We synthesized and evaluated the proposed enhancement in terms of power dissipation and area. Our results indicate that the impact of necessary alterations to the fabric is negligible and effects the data transfer between the fabric and the periphery only marginally.

Crumpling and second sound in lyotropic lamellar phases

We study relative concentration fluctuations in two component lamellar smectic liquid crystals consisting of surfactant layers of width w separated by a background fluid and show that these fluctuations are dominated by crumpling fluctuations of the surfactant layers when (w/l)2

Hydrodynamics of the Renn-Lubensky twist grain boundary phase, and the decoupled lamellar phase

The long-wavelength hydrodynamics of the Renn-Lubensky twist grain boundary phase with grain boundary angle 2pialpha, alpha irrational, is studied. We find three propagating sound modes, with two of the three sound speeds vanishing for propagation orthogonal to the grains, and one vanishing for propagation parallel to the grains as well. In addition, we find that the viscosities eta1, eta2, eta4, and eta5 diverge like 1/Absolute value of omega as frequency omega --> 0, with the divergent parts DELTAeta(i) satisfying DELTAeta1DELTAeta4=(DELTAeta5)2, exactly. Our results should also apply to the predicted decoupled lamellar phase.

Energy-Efficient Fault Tolerance in Chip Multiprocessors Using Critical Value Forwarding

Relentless CMOS scaling coupled with lower design tolerances is making ICs increasingly susceptible to wear-out related permanent faults and transient faults, necessitating on-chip fault tolerance in future chip microprocessors (CMPs). In this paper we introduce a new energy-efficient fault-tolerant CMP architecture known as Redundant Execution using Critical Value Forwarding (RECVF). RECVF is based on two observations: (i) forwarding critical instruction results from the leading to the trailing core enables the latter to execute faster, and (ii) this speedup can be exploited to reduce energy consumption by operating the trailing core at a lower voltage-frequency level. Our evaluation shows that RECVF consumes 37% less energy than conventional dual modular redundant (DMR) execution of a program. It consumes only 1.26 times the energy of a non-fault-tolerant baseline and has a performance overhead of just 1.2%.

Shear alignment of a disordered lamellar mesophase

The shear alignment of an initially disordered lamellar phase is examined using lattice Boltzmann simulations of a mesoscopic model based on a free-energy functional for the concentration modulation. For a small shear cell of width 8 lambda, the qualitative features of the alignment process are strongly dependent on the Schmidt number Sc = nu/D (ratio of kinematic viscosity and mass diffusion coefficient). Here, lambda is the wavelength of the concentration modulation. At low Schmidt number, it is found that there is a significant initial increase in the viscosity, coinciding with the alignment of layers along the extensional axis, followed by a decrease at long times due to the alignment along the flow direction. At high Schmidt number, alignment takes place due to the breakage and reformation of layers because diffusion is slow compared to shear deformation; this results in faster alignment. The system size has a strong effect on the alignment process; perfect alignment takes place for a small systems of width 8 lambda and 16 lambda, while a larger system of width 32 lambda does not align completely even at long times. In the larger system, there appears to be a dynamical steady state in which the layers are not perfectly aligned-where there is a balance between the annealing of defects due to shear and the creation due to an instability of the aligned lamellar phase under shear. We observe two types of defect creation mechanisms: the buckling instability under dilation, which was reported earlier, as well as a second mechanism due to layer compression.

Non-Linear effects of membrane fluctuations in the dilute lamellar phase

The static structure factor of the dilute sterically stabilised lamellar phase is calculated and found to have an Ornstein-Zernike form with a correlation length that diverges at infinite dilution. The relaxation time for concentration fluctuations at large wave number q is shown to go as q-3 with a coefficient independent of the membrane bending rigidity. The membrane fluctuations also give rise to strongly frequency-dependent viscosities at high frequencies.

A portable battery-operated chip thermocycler based on induction heating

A microchip thermocycler, fabricated from silicon and Pyrex #7740 glass, is described. Usual resistive heating has been replaced by induction heating, leading to much simpler fabrication steps. Heating and cooling rates of 6.5 and 4.2 degreesC/s, respectively have been achieved, by optimising the heater dimensions and heating frequency (similar to200 kHz). Four devices are mounted on a heater, resulting in low power consumption (similar to 1.4 W per device on the average). Using simple on-off electronic temperature control, a temperature stability within -0.2 degreesC is achieved. Features such as induction heating, good temperature control, battery operation, and low power consumption make the device suitable for portable applications, particularly in polymerase chain reaction (PCR) systems. (C) 2002 Elsevier Science B.V. All rights reserved.

A System-C based Micro architectural Exploration Framework for Latency, Power and Performance Trade-offs of On-Chip Interconnection

We describe a System-C based framework we are developing, to explore the impact of various architectural and microarchitectural level parameters of the on-chip interconnection network elements on its power and performance. The framework enables one to choose from a variety of architectural options like topology, routing policy, etc., as well as allows experimentation with various microarchitectural options for the individual links like length, wire width, pitch, pipelining, supply voltage and frequency. The framework also supports a flexible traffic generation and communication model. We provide preliminary results of using this framework to study the power, latency and throughput of a 4x4 multi-core processing array using mesh, torus and folded torus, for two different communication patterns of dense and sparse linear algebra. The traffic consists of both Request-Response messages (mimicing cache accesses)and One-Way messages. We find that the average latency can be reduced by increasing the pipeline depth, as it enables higher link frequencies. We also find that there exists an optimum degree of pipelining which minimizes energy-delay product.