Linear time geometrical design rule checker based on quadtree representation of VLSI mask layouts

An efficient geometrical design rule checker is proposed, based on operations on quadtrees, which represent VLSI mask layouts. The time complexity of the design rule checker is O(N), where N is the number of polygons in the mask. A pseudoPascal description is provided of all the important algorithms for geometrical design rule verification.

High performance VLSI architecture design for H.264 CAVLC decoder

H.264 video standard achieves high quality video along with high data compression when compared to other existing video standards. H.264 uses context-based adaptive variable length coding (CAVLC) to code residual data in Baseline profile. In this paper we describe a novel architecture for CAVLC decoder including coeff-token decoder, level decoder total-zeros decoder and run-before decoder UMC library in 0.13 mu CMOS technology is used to synthesize the proposed design. The proposed design reduces chip area and improves critical path performance of CAVLC decoder in comparison with [1]. Macroblock level (including luma and chroma) pipeline processing for CAVLC is implemented with an average of 141 cycles (including pipeline buffering) per macroblock at 250MHz clock frequency. To compare our results with [1] clock frequency is constrained to 125MHz. The area required for the proposed architecture is 17586 gates, which is 22.1% improvement in comparison to [1]. We obtain a throughput of 1.73 * 10(6) macroblocks/second, which is 28% higher than that reported in [1]. The proposed design meets the processing requirement of 1080HD [5] video at 30frames/seconds.

Design and implementation of a PC-based FPGA tester

A new range of programmable logic devices are revolutionizing the way complex digital hardware is designed and built all over the world. Being able to test these devices in order to validate and dynamically improve on the design is crucial. This paper describes a low-cost FPGA tester that can test SRAM based FPGAs in the laboratory.

Design and realization of high-performance wave-pipelined 8×8 b multiplier in CMOS technology

Wave pipelining is a design technique for increasing the throughput of a digital circuit or system without introducing pipelining registers between adjacent combinational logic blocks in the circuit/system. However, this requires balancing of the delays along all the paths from the input to the output which comes the way of its implementation. Static CMOS is inherently susceptible to delay variation with input data, and hence, receives a low priority for wave pipelined digital design. On the other hand, ECL and CML, which are amenable to wave pipelining, lack the compactness and low power attributes of CMOS. In this paper we attempt to exploit wave pipelining in CMOS technology. We use a single generic building block in Normal Process Complementary Pass Transistor Logic (NPCPL), modeled after CPL, to achieve equal delay along all the propagation paths in the logic structure. An 8×8 b multiplier is designed using this logic in a 0.8 ?m technology. The carry-save multiplier architecture is modified suitably to support wave pipelining, viz., the logic depth of all the paths are made identical. The 1 mm×0.6 mm multiplier core supports a throughput of 400 MHz and dissipates a total power of 0.6 W. We develop simple enhancements to the NPCPL building blocks that allow the multiplier to sustain throughputs in excess of 600 MHz. The methodology can be extended to introduce wave pipelining in other circuits as well

Escape of high mass ions due to initial thermal energy and its implications for axially symmetric RF ion trap mass analyzer design

This paper investigates the loss of high mass ions due to their initial thermal energy in ion trap mass analyzers. It provides an analytical expression for estimating the percentage loss of ions of a given mass at a particular temperature, in a trap operating under a predetermined set of conditions. The expression we developed can be used to study the loss of ions due to its initial thermal energy in traps which have nonlinear fields as well as those which have linear fields. The expression for the percentage of ions lost is shown to be a function of the temperature of the ensemble of ions, ion mass and ion escape velocity. An analytical expression for the escape velocity has also been derived in terms of the trapping field, drive frequency and ion mass. Because the trapping field is determined by trap design parameters and operating conditions, it has been possible to study the influence of these parameters on ion loss. The parameters investigated include ion temperature, magnitude of the initial potential applied to the ring electrode (which determines the low mass cut-off), trap size, dimensions of apertures in the endcap electrodes and RF drive frequency. Our studies demonstrate that ion loss due to initial thermal energy increases with increase in mass and that, in the traps investigated, ion escape occurs in the radial direction. Reduction in the loss of high mass ions is favoured by lower ion temperatures, increasing low mass cut-off, increasing trap size, and higher RF drive frequencies. However, dimensions of the apertures in the endcap electrodes do not influence ion loss in the range of aperture sizes considered. (C) 2010 Elsevier B.V. All rights reserved.

Streaming FFT on REDEFINE-v2: An Application-Architecture Design Space Exploration

In this paper we explore an implementation of a high-throughput, streaming application on REDEFINE-v2, which is an enhancement of REDEFINE. REDEFINE is a polymorphic ASIC combining the flexibility of a programmable solution with the execution speed of an ASIC. In REDEFINE Compute Elements are arranged in an 8x8 grid connected via a Network on Chip (NoC) called RECONNECT, to realize the various macrofunctional blocks of an equivalent ASIC. For a 1024-FFT we carry out an application-architecture design space exploration by examining the various characterizations of Compute Elements in terms of the size of the instruction store. We further study the impact by using application specific, vectorized FUs. By setting up different partitions of the FFT algorithm for persistent execution on REDEFINE-v2, we derive the benefits of setting up pipelined execution for higher performance. The impact of the REDEFINE-v2 micro-architecture for any arbitrary N-point FFT (N > 4096) FFT is also analyzed. We report the various algorithm-architecture tradeoffs in terms of area and execution speed with that of an ASIC implementation. In addition we compare the performance gain with respect to a GPP.

Is The Burden of Medical Education Affecting Ethics of Medical Treatment?

A substantial number of medical students in India have to bear an enormous financial burden for earning a bachelor's degree in medicine referred to as MBBS (bachelor of medicine and bachelor of surgery). This degree program lasts for four and one-half years followed by one year of internship. A postgraduate degree, such as MD, has to be pursued separately on completion of a MBBS. Every medical college in India is part of a hospital where the medical students get clinical exposure during the course of their study. All or at least a number of medical colleges in a given state are affiliated to a university that mainly plays a role of an overseeing authority. The medical colleges usually have no official interaction with other disciplines of education such as science and engineering, perhaps because of their independent location and absence of emphasis on medical research. However, many of the medical colleges are adept in imparting high-quality and sound training in medical practices including diagnostics and treatment. The medical colleges in India are generally of two types, i.e., government owned and private. Since only a limited number of seats are available across India in the former category of colleges, only a small fraction of aspiring candidates can find admission in these colleges after performing competitively in the relevant entrance tests. A major advantage of studying in these colleges is the nominal tuition fees that have to be paid. On the other hand, a large majority of would-be medical graduates have to seek admission in the privately run medical institutes in which the tuition and other related fees can be mind boggling when compared to their public counterparts. Except for candidates of exceptionally affluent background, the only alternative for fulfilling the dream of becoming a doctor is by financing one's study through hefty bank loans that may take years to pay back. It is often heard from patients that they are asked by doctors to undergo a plethora of diagnostic tests for apparently minor illnesses, which may financially benefit those prescribing the tests. The present paper attempts to throw light on the extent of disparity in cost of a medical education between state-funded and privately managed medical colleges in India; the average salary of a new medical graduate, which is often ridiculously low when compared to what is offered in entry-level engineering and business jobs; and the possible repercussions of this apparently unjust economic situation regarding the exploitation of patients.

Design of a Low Power 64 Point FFT Architecture for WLAN Applications

This paper presents a Radix-4(3) based FFT architecture suitable for OFDM based WLAN applications. The radix-4(3) parallel unrolled architecture presented here, uses a radix-4 butterfly unit which takes all four inputs in parallel and can selectively produce one out of the four outputs. A 64 point FFT processor based on the proposed architecture has been implemented in UMC 130nm 1P8M CMOS process with a maximum clock frequency of 100 MHz and area of 0.83mm(2). The proposed processor provides a throughput of four times the clock rate and can finish one 64 point FFT computation in 16 clock cycles. For IEEE 802.11a/g WLAN, the processor needs to be operated at a clock rate of 5 MHz with a power consumption of 2.27 mW which is 27% less than the previously reported low power implementations.

Conserved water-mediated recognition and dynamics of NAD(+) (carboxamide group) to hIMPDH enzyme: water mimic approach toward the design of isoform-selective inhibitor

Inosine monophosphate dehydrogenase (IMPDH) enzyme involves in GMP biosynthesis pathway. Type I hIMPDH is expressed at lower levels in all cells, whereas type II is especially observed in acute myelogenous leukemia, chronic myelogenous leukemia cancer cells, and 10 ns simulation of the IMP-NAD(+) complex structures (PDB ID. 1B3O and 1JCN) have revealed the presence of a few conserved hydrophilic centers near carboxamide group of NAD(+). Three conserved water molecules (W1, W, and W1 `) in di-nucleotide binding pocket of enzyme have played a significant role in the recognition of carboxamide group (of NAD(+)) to D274 and H93 residues. Based on H-bonding interaction of conserved hydrophilic (water molecular) centers within IMP-NAD(+)-enzyme complexes and their recognition to NAD(+), some covalent modification at carboxamide group of di-nucleotide (NAD(+)) has been made by substituting the -CONH(2)group by -CONHNH2 (carboxyl hydrazide group) using water mimic inhibitor design protocol. The modeled structure of modified ligand may, though, be useful for the development of antileukemic agent or it could be act as better inhibitor for hIMPDH-II.