Linear time geometrical design rule checker based on quadtree representation of VLSI mask layouts
Data(s) |
01/09/1986
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Resumo |
An efficient geometrical design rule checker is proposed, based on operations on quadtrees, which represent VLSI mask layouts. The time complexity of the design rule checker is O(N), where N is the number of polygons in the mask. A pseudoPascal description is provided of all the important algorithms for geometrical design rule verification. |
Formato |
application/pdf |
Identificador |
Nandy, SK and Patnaik, LM (1986) Linear time geometrical design rule checker based on quadtree representation of VLSI mask layouts. In: Computer-Aided Design, 18 (7). 380 -388. |
Publicador |
Elsevier Science |
Relação |
http://www.sciencedirect.com/science?_ob=MImg&_imagekey=B6TYR-482B039-YK-1&_cdi=5625&_user=512776&_orig=search&_coverDate=09%2F30%2F1986&_sk=999819992&view=c&wchp=dGLzVtb-zSkzk&md5=f7f0e10a600a5b168b41786702db7bd0&ie=/sdarticle.pdf http://eprints.iisc.ernet.in/20880/ |
Palavras-Chave | #Supercomputer Education & Research Centre |
Tipo |
Journal Article PeerReviewed |