A Combination of Hexagonal and 12-Sided Polygonal Voltage Space Vector PWM Control for IM Drives Using Cascaded Two-Level Inverters

This paper proposes a multilevel inverter configuration which produces a hexagonal voltage space vector structure in the lower modulation region and a 12-sided polygonal space vector structure in the overmodulation region. A conventional multilevel inverter produces 6n plusmn 1 (n = odd) harmonics in the phase voltage during overmodulation and in the extreme square-wave mode of operation. However, this inverter produces a 12-sided polygonal space vector location, leading to the elimination of 6n plusmn 1 (n = odd) harmonics in the overmodulation region extending to a final 12-step mode of operation with a smooth transition. The benefits of this arrangement are lower losses and reduced torque pulsation in an induction motor drive fed from this converter at higher modulation indexes. The inverter is fabricated by using three conventional cascaded two-level inverters with asymmetric dc-bus voltages. A comparative simulation study of the harmonic distortion in the phase voltage and associated losses in conventional multilevel inverters and that of the proposed inverter is presented in this paper. Experimental validation on a prototype shows that the proposed converter is suitable for high-power applications because of low harmonic distortion and low losses.

Novel CMOS Schmitt trigger

A novel CMOS Schmitt trigger using only four MOS transistors is discussed. This circuit, which works on the principle of load-coupled regenerative feedback, can be implemented using conventional CMOS technology with only one extra fabrication step. It can be implemented even more easily in CMOS/SOS (silicon-on-sapphire) integrated circuits. The hysteresis of this Schmitt trigger can be controlled by a proper choice of the transistor geometries.

A New PWM Control Method for Three-Phase Autosequentially Commutated Current Source Inverters

A new current pulsewidth modulation (PWM) method is presented which uses the principle of creating zero three-phase currents at selected instants of time, through which the load current harmonic content can be controlled along with the magnitude of its fundamental content. This gives rise to reduction of motor torque ripples through the selection of suitable PWM patterns and a fast current control in the inverter by varying the pulsewidths of the PWM pattern. Under this new PWM mode of operation, the autosequentially commutated inverter (ASCI) circuit can be modified easily so that a higher number of pulses can be accomodated within a half-cycle, compared to the normal ASCI circuit. The experimental oscillograms verify the effectiveness of the new PWM method.

Harmonics in voltage-source PWM inverters

he performance of an induction motor fed by PWM inverters is mainly determined by the harmonic contents of the output voltage. This paper presents a method of numerically calculating the harmonics in the output voltage waveform. Equal pulse-width modulation and siunsoidal PWM are studied. Analysis has been done for single-phase and three-phase bridge inverters. A systematic procedure is given for computing the harmonics and the results are. tabulated.

Protection and Switching-Aid Networks for Transistor Bridge Inverters

The present trend in the industry is towards the use of power transistors in the development of efficient Pulsewidth Modulated (PWM) inverters, because of their operation at high frequency, simplicity of turn-off, and low commutation losses compared to the technology using thyristors. But the protection of power transistors, minimization of switching power loss, and design of base drive circuit are very important for a reliable operation of the system. The requirements, analysis, and a simplified procedure for calculation of the switching-aid network components are presented. The transistor is protected against short circuit using a modified autoregulated and autoprotection drive circuit. The experimental results show that the switching power loss and voltage stress in the device can be reduced by suitable choice of the switching-aid network component values.

LPG Gas-Sensing System With SnO2 Thin-Film Transducer and 0.7-mu m CMOS Signal Conditioning ASIC

The design and implementation of a complete gas sensor system for liquified petroleum gas (LPG) gas sensing are presented. The system consists of a SnO2 transducer, a lowcost heater, an application specific integrated circuit (ASIC) with front-end interface circuitry, and a microcontroller interface for data logging. The ASIC includes a relaxation-oscillator-based heater driver circuit that is capable of controlling the sensor operating temperature from 100degC to 425degC. The sensor readout circuit in the ASIC, which is based on the resistance to time conversion technique, has been designed to measure the gas sensor response over three orders of resistance change during its interaction with gases.

Integrated CMOS Gas Sensors

We present a low power gas sensor system on CMOS platform consisting of micromachined polysilicon microheater, temperature controller circuit, resistance readout circuit and SnO2 transducer film. The design criteria for different building blocks of the system is elaborated The microheaters are optimized for temperature uniformity as well as static and dynamic response. The electrical equivalent model for the microheater is derived by extracting thermal and mechanical poles through extensive laser doppler vibrometer measurements. The temperature controller and readout circuit are realized on 130nm CMOS technology The temperature controller re-uses the heater as a temperature sensor and controls the duty cycle of the waveform driving the gate of the power MOSFET which supplies heater current. The readout circuit, with subthreshold operation of the MOSFETs, is based oil resistance to time period conversion followed by frequency to digital converter Subthreshold operatin of MOSFETs coupled with sub-ranging technique, achieves ultra low power consumption with more than five orders of magnitude dynamic range RF sputtered SnO2 film is optimized for its microstructure to achive high sensitivity to sense LPG gas.

Multilevel Dodecagonal Space Vector Generation for Open-end Winding Induction Motor Drive Using Conventional Three Level Inverters

A novel dodecagonal space vector structure for induction motor drive is presented in this paper. It consists of two dodecagons, with the radius of the outer one twice the inner one. Compared to existing dodecagonal space vector structures, to achieve the same PWM output voltage quality, the proposed topology lowers the switching frequency of the inverters and reduces the device ratings to half. At the same time, other benefits obtained from existing dodecagonal space vector structure are retained here. This includes the extension of the linear modulation range and elimination of all 6+/-1 harmonics (n=odd) from the phase voltage. The proposed structure is realized by feeding an open-end winding induction motor with two conventional three level inverters. A detailed calculation of the PWM timings for switching the space vector points is also presented. Simulation and experimental results indicate the possible application of the proposed idea for high power drives.

Modeling and Analysis of Noise Margin in SET Logic

In this paper the static noise margin for SET (single electron transistor) logic is defined and compact models for the noise margin are developed by making use of the MIB (Mahapatra-Ionescu-Banerjee) model. The variation of the noise margin with temperature and background charge is also studied. A chain of SET inverters is simulated to validate the definition of various logic levels (like VIH, VOH, etc.) and noise margin. Finally the noise immunity of SET logic is compared with current CMOS logic.

Process variability-aware statistical hybrid modeling of dynamic power dissipation in 65 nm CMOS designs

A generalized technique is proposed for modeling the effects of process variations on dynamic power by directly relating the variations in process parameters to variations in dynamic power of a digital circuit. The dynamic power of a 2-input NAND gate is characterized by mixed-mode simulations, to be used as a library element for 65mn gate length technology. The proposed methodology is demonstrated with a multiplier circuit built using the NAND gate library, by characterizing its dynamic power through Monte Carlo analysis. The statistical technique of Response. Surface Methodology (RSM) using Design of Experiments (DOE) and Least Squares Method (LSM), are employed to generate a "hybrid model" for gate power to account for simultaneous variations in multiple process parameters. We demonstrate that our hybrid model based statistical design approach results in considerable savings in the power budget of low power CMOS designs with an error of less than 1%, with significant reductions in uncertainty by atleast 6X on a normalized basis, against worst case design.

Linear transconductor with flipped voltage follower in 130 nm CMOS

This paper presents a modified design method for linear transconductor circuit in 130 nm CMOS technology to improve linearity, robustness against process induced threshold voltage variability and reduce harmonic distortion. Source follower in the adaptively biased differential pair (ABDP) linear transconductor circuit is replaced with flipped voltage follower to improve the efficiency of the tail current source, which is connected to a conventional differential pair. The simulation results show the performance of the modified circuit also has better speed, noise performance and common mode rejection ratio compared to the ABDP circuit.

A Survey on Cascaded Multilevel Inverters

Cascaded multilevel inverters synthesize a medium-voltage output based on a series connection of power cells which use standard low-voltage component configurations. This characteristic allows one to achieve high-quality output voltages and input currents and also outstanding availability due to their intrinsic component redundancy. Due to these features, the cascaded multilevel inverter has been recognized as an important alternative in the medium-voltage inverter market. This paper presents a survey of different topologies, control strategies and modulation techniques used by these inverters. Regenerative and advanced topologies are also discussed. Applications where the mentioned features play a key role are shown. Finally, future developments are addressed.

An Integrated Design Procedure for High Frequency AC Inductors for Inverters

Inductors are important energy storage elements that are used as filters in switching power converters. The operating efficiency of power inductors depend on the initial design choices and they remain as one of the most inefficient elements in a power converter. The focus of this paper is to explore the inductor design procedure from the point of efficiency and operating temperature. A modified form of the area product approach is used as starting point for the inductor design. The equations which estimate the power loss in core and copper winding are described. The surface temperature of the inductor is modelled using heat transfer equations for radiation and natural convection. All design assumptions are verified by actual experimental data and results show a good match with the analysis.

A Simple Five-Level Inverter Topology for Induction Motor Drive Using Conventional Two-Level Inverters and Flying Capacitor Technique

This paper proposes a new five-level inverter topology for open-end winding induction motor (IM) drive. The popular existing circuit configurations for five-level inverter include the NPC inverter and flying capacitor topologies. Compared to the NPC inverter, the proposed topology eliminates eighteen clamping diodes having different voltage ratings in the present circuit. Moreover it requires only one capacitor bank per phase, whereas flying capacitor schemes for five level topologies require six capacitor banks per phase. The proposed topology is realized by feeding the phase winding of an open-end induction motor with two-level inverters in series with flying capacitors. The flying capacitor voltages are balanced using the switching state redundancy for full modulation range. The proposed inverter scheme is capable of producing two-level to five-level pulse width modulated voltage across the phase winding depending on the modulation range. Additionally, in case of any switch failure in the flying capacitor connection, the proposed inverter topology can be operated as a three-level inverter for full modulation range. The proposed scheme is experimentally verified on a four pole, 5hp induction motor drive.