Design and evaluation of a dual-microcomputer shared memory system with a shared I/O bus

The design, implementation and evaluation are described of a dual-microcomputer system based on the concept of shared memory. Shared memory is useful for passing large blocks of data and it also provides a means to hold and work with shared data. In addition to the shared memory, a separate bus between the I/O ports of the microcomputers is provided. This bus is utilized for interprocessor synchronization. Software routines helpful in applying the dual-microcomputer system to realistic problems are presented. Performance evaluation of the system is carried out using benchmarks.

A Modified Heffron-Phillip's Model for The Design of Power System Stabilizers

In this paper a modified Heffron-Phillip's (K-constant) model is derived for the design of power system stabilizers. A knowledge of external system parameters, such as equivalent infinite bus voltage and external impedances or their equivalent estimated values is required for designing a conventional power system stabilizer. In the proposed method, information available at the secondary bus of the step-up transformer is used to set up a modified Heffron-Phillip's (ModHP) model. The PSS design based on this model utilizes signals available within the generating station. The efficacy of the proposed design technique and the performance of the stabilizer has been evaluated over a range of operating and system conditions. The simulation results have shown that the performance of the proposed stabilizer is comparable to that could be obtained by conventional design but without the need for the estimation and computation of external system parameters. The proposed design is thus well suited for practical applications to power system stabilization, including possibly the multi-machine applications where accurate system information is not readily available.

Optimal Interconnections in the Design of Microprocessors and Digital Systems

This paper recasts the multiple data path assignment problem solved by Torng and Wilhelm by the dynamic programming method [1] into a minimal covering problem following a switching theoretic approach. The concept of bus compatibility for the data transfers is used to obtain the various ways of interconnecting the circuit modules with the minimum number of buses that allow concurrent data transfers. These have been called the feasible solutions of the problem. The minimal cost solutions are obtained by assigning weights to the bus-compatible sets present in the feasible solutions. Minimization of the cost of the solution by increasing the number of buses is also discussed.

Optimal Interconnections in the Design of Microprocessors and Digital Systems

This paper recasts the multiple data path assignment problem solved by Torng and Wilhelm by the dynamic programming method [1] into a minimal covering problem following a switching theoretic approach. The concept of bus compatibility for the data transfers is used to obtain the various ways of interconnecting the circuit modules with the minimum number of buses that allow concurrent data transfers. These have been called the feasible solutions of the problem. The minimal cost solutions are obtained by assigning weights to the bus-compatible sets present in the feasible solutions. Minimization of the cost of the solution by increasing the number of buses is also discussed.

Single network adaptive critic design for power system stabilisers

The recently developed single network adaptive critic (SNAC) design has been used in this study to design a power system stabiliser (PSS) for enhancing the small-signal stability of power systems over a wide range of operating conditions. PSS design is formulated as a discrete non-linear quadratic regulator problem. SNAC is then used to solve the resulting discrete-time optimal control problem. SNAC uses only a single critic neural network instead of the action-critic dual network architecture of typical adaptive critic designs. SNAC eliminates the iterative training loops between the action and critic networks and greatly simplifies the training procedure. The performance of the proposed PSS has been tested on a single machine infinite bus test system for various system and loading conditions. The proposed stabiliser, which is relatively easier to synthesise, consistently outperformed stabilisers based on conventional lead-lag and linear quadratic regulator designs.

Design and analysis of ARROW-based racetrack resonator vibration sensor for inertial navigation application

In this paper we propose and analyze a novel racetrack resonator based vibration sensor for inertial grade application. The resonator is formed with an Anti Resonance Reflecting Optical Waveguide (ARROW) structure which offers the advantage of low loss and single mode propagation. The waveguide is designed to operate at 1310nm and TM mode of propagation since the Photo-elastic co-efficient is larger than TE mode in a SiO2/ Si3N4/ SiO2. The longer side of the resonator is placed over a cantilever beam with a proof mass. A single bus waveguide is coupled to the resonator structure. When the beam vibrates the resonator arm at the foot of the cantilever experiences maximum stress. Due to opto-mechanical coupling the effective refractive index of the resonator changes hence the resonance wavelength shifts. The non uniform cantilever beam has a dimension of 1.75mm X 0.45mm X 0.020mm and the proof mass has a dimension of 3mm X 3mm X 0.380mm. The proof mass lowers the natural frequency of vibration to 410Hz, hence designed for inertial navigation application. The operating band of frequency is from DC to 100Hz and acceleration of less than 1g. The resonator has a Free Spectral Range (FSR) of 893pm and produces a phase change of 22.4mrad/g.

Power Optimal Network-on-Chip Interconnect Design

A large part of today's multi-core chips is interconnect. Increasing communication complexity has made essential new strategies for interconnects, such as Network on Chip. Power dissipation in interconnects has become a substantial part of the total power dissipation. Techniques to reduce interconnect power have thus become a necessity. In this paper, we present a design methodology that gives values of bus width for interconnect links, frequency of operation for routers, in Network on Chip scenario that satisfy required throughput and dissipate minimal switching power. We develop closed form analytical expressions for the power dissipation, with bus width and frequency as variables and then use Lagrange multiplier method to arrive at the optimal values. We present a 4 port router in 90 nm technology library as case study. The results obtained from analysis are discussed.

Power System Stabilizers Design for Interconnected Power Systems

This paper proposes a method of designing fixed parameter decentralized power system stabilizers (PSS) for interconnected multi-machine power systems. Conventional design technique using a single machine infinite bus approximation involves the frequency response estimation called the GEP(s) between the AVR input and the resultant electrical torque. This requires the knowledge of equivalent external reactance and infinite bus voltage or their estimated values at each machine. Other design techniques using P-Vr characteristics or residues are based on complete system information. In the proposed method, information available at the high voltage bus of the step-up transformer is used to set up a modified Heffron-Phillip's model. With this model it is possible to decide the structure of the PSS compensator and tune its parameters at each machine in the multi-machine environment, using only those signals that are available at the generating station. The efficacy of the proposed design technique has been evaluated on three of the most widely used test systems. The simulation results have shown that the performance of the proposed stabilizer is comparable to that which could be obtained by conventional design but without the need for the estimation and computation of external system parameters.

Common mode DC bus filter for Active Front-End converter

Active Front-End (AFE) converter operation produces electrically noisy DC bus on common mode basis. This results in higher ground current as compared to three phase diode bridge rectifier. Filter topologies for DC bus have to deal problems with switching frequency and harmonic currents. The proposed filter approach reduces common mode voltage and circulates third harmonic current within the system, resulting in minimal ground current injection. The filtering technique, its constrains and design to attenuate common mode voltage and eliminate lower order harmonics injection to ground is discussed. The experimental results for operation of the converter with both SPWM and CSVPWM are presented.

Low-frequency dc bus ripple cancellation in single phase pulse-width modulation inverters

This study presents a topology for a single-phase pulse-width modulation (PWM) converter which achieves low-frequency ripple reduction in the dc bus even when there are grid frequency variations. A hybrid filter is introduced to absorb the low-frequency current ripple in the dc bus. The control strategy for the proposed filter does not require the measurement of the dc bus ripple current. The design criteria for selecting the filter components are also presented in this study. The effectiveness of the proposed circuit has been tested and validated experimentally. A smaller dc-link capacitor is sufficient to keep the low-frequency bus ripple to an acceptable range in the proposed topology.

A controller design method for 3 phase 4 wire grid connected VSI with LCL filter

Closed loop control of a grid connected VSI requires line current control and dc bus voltage control. The closed loop system comprising PR current controller and grid connected VSI with LCL filter is a higher order system. Closed loop control gain expressions are therefore difficult to obtain directly for such systems. In this work a simplified approach has been adopted to find current and voltage controller gain expressions for a 3 phase 4 wire grid connected VSI with LCL filter. The closed loop system considered here utilises PR current controller in natural reference frame and PI controller for dc bus voltage control. Asymptotic frequency response plot and gain bandwidth requirements of the system have been used for current control and voltage controller design. A simplified lower order model, derived for closed loop current control, is used for the dc bus voltage controller design. The adopted design method has been verified through experiments by comparison of the time domain response.