Low threshold voltage ZnO thin film transistor with a Zn0.7Mg0.3O gate dielectric for transparent electronics

A highly transparent all ZnO thin film transistor (ZnO-TFT) with a transmittance of above 80% in the visible part of the spectrum, was fabricated by direct current magnetron sputtering, with a bottom gate configuration. The ZnO-TFT with undoped ZnO channel layers deposited on 300 nm Zn0.7Mg0.3O gate dielectric layers attains an on/off ratio of 104 and mobility of 20 cm2/V s. The capacitance-voltage (C−V) characteristics of the ZnO-TFT exhibited a transition from depletion to accumulation with a small hysteresis indicating the presence of oxide traps. The trap density was also computed from the Levinson’s plot. The use of Zn0.7Mg0.3O as a dielectric layer adds additional dimension to its applications. The room temperature processing of the device depicts the possibility of the use of flexible substrates such as polymer substrates. The results provide the realization of transparent electronics for next-generation optoelectronics.

Synthesis of liquid crystalline benzothiazole base derivatives: A study of their optical and electrical properties

Two new donor-acceptor type liquid crystalline semiconductors based on benzothiazole have been synthesized. Their structural, photophysical and electronic properties were investigated using X-ray diffraction, atomic force microscopy, cyclic voltammetry, UV-Vis, photoluminescence, and Raman spectroscopy. The liquid crystalline behaviour of the molecules was thoroughly examined by differential scanning calorimetry (DSC) and optical polarizing microscope. The DSC and thermogravimetric analysis (TGA) show that these materials posses excellent thermal stability and have decomposition temperatures in excess of 300 degrees C. Beyond 160 degrees C both molecules show a smectic A liquid crystalline phase that exists till about 240 degrees C. Field-effect transistors were fabricated by vacuum evaporating the semiconductor layer using standard bottom gate/top contact geometry. The devices exhibit p-channel behaviour with hole mobilities of 10(-2) cm(2)/Vs. (C) 2009 Elsevier B.V. All rights reserved.

An Advanced Gate Driver for Insulated Gate Bipolar Transistors to Eliminate Dead-time Induced Distortions in Inverter Output

Dead-time is introduced between the gating signals to the top and bottom switches in a voltage source inverter (VSI) leg, to prevent shoot through fault due to the finite turn-off times of IGBTs. The dead-time results in a delay when the incoming device is an IGBT, resulting in error voltage pulses in the inverter output voltage. This paper presents the design, fabrication and testing of an advanced gate driver, which eliminates dead-time and consequent output distortion. Here, the gating pulses are generated such that the incoming IGBT transition is not delayed and shoot-through is also prevented. The various logic units of the driver card and fault tolerance of the driver are verified through extensive tests on different topologies such as chopper, half-bridge and full-bridge inverter, and also at different conditions of load. Experimental results demonstrate the improvement in the load current waveform quality with the proposed circuit, on account of elimination of dead-time.

Modeling of Channel Potential and Subthreshold Slope of Symmetric Double-Gate Transistor

A new physically based classical continuous potential distribution model, particularly considering the channel center, is proposed for a short-channel undoped body symmetrical double-gate transistor. It involves a novel technique for solving the 2-D nonlinear Poisson's equation in a rectangular coordinate system, which makes the model valid from weak to strong inversion regimes and from the channel center to the surface. We demonstrated, using the proposed model, that the channel potential versus gate voltage characteristics for the devices having equal channel lengths but different thicknesses pass through a single common point (termed ``crossover point''). Based on the potential model, a new compact model for the subthreshold swing is formulated. It is shown that for the devices having very high short-channel effects (SCE), the effective subthreshold slope factor is mainly dictated by the potential close to the channel center rather than the surface. SCEs and drain-induced barrier lowering are also assessed using the proposed model and validated against a professional numerical device simulator.

Within-Die Gate Delay Variability Measurement using Re-configurable Ring Oscillator

We report a circuit technique to measure the on-chip delay of an individual logic gate (both inverting and non-inverting) in its unmodified form using digitally reconfigurable ring oscillator (RO). Solving a system of linear equations with different configuration setting of the RO gives delay of an individual gate. Experimental results from a test chip in 65nm process node show the feasibility of measuring the delay of an individual inverter to within 1pS accuracy. Delay measurements of different nominally identical inverters in close physical proximity show variations of up to 26% indicating the large impact of local or within-die variations.

Within-Die Gate Delay Variability Measurement Using Reconfigurable Ring Oscillator

We report the design and characterization of a circuit technique to measure the on-chip delay of an individual logic gate (both inverting and noninverting) in its unmodified form. The test circuit comprises of digitally reconfigurable ring oscillator (RO). The gate under test is embedded in each stage of the ring oscillator. A system of linear equations is then formed with different configuration settings of the RO, relating the individual gate delay to the measured period of the RO, whose solution gives the delay of the individual gates. Experimental results from a test chip in 65-nm process node show the feasibility of measuring the delay of an individual inverter to within 1 ps accuracy. Delay measurements of different nominally identicall inverters in close physical proximity show variations of up to 28% indicating the large impact of local variations. As a demonstration of this technique, we have studied delay variation with poly-pitch, length of diffusion (LOD) and different orientations of layout in silicon. The proposed technique is quite suitable for early process characterization, monitoring mature process in manufacturing and correlating model-to-hardware.

The effect of bottom reflectivity on the performance of a solar pond

The reflectivity of the bottom of a solar pond increases on account of the accumulation of dirt or the presence of undissolved salt. The effect of the reflection of the solar radiation at the bottom of the pond on the seasonal performance of the pond has been studied using a three zone model. The spectral reflectivity of dirt and common salt were measured in the laboratory and used in the analysis. The results obtained from the analysis show that the presence of dirt at the bottom of the pond does not affect the performance of the pond substantially. On the other hand, the presence of undissolved salt at the bottom of the pond results in substantial deterioration of the pond performance.

RF Sputtered Er2O3 Thin Films as High-k Gate Dielectrics for Germanium MOS Devices

We report the material and electrical properties of Erbium Oxide (Er2O3) thin films grown on n-Ge (100) by RF sputtering. The properties of the films are correlated with the processing conditions. The structural characterization reveals that the films annealed at 550 degrees C, has densified as compared to the as-grown ones. Fixed oxide charges and interface charges, both of the order of 10(13)/cm(2) is observed.

Effect of Bottom Bubbling Conditions on Surface Reaction Rate in Oxygen-Water System

In secondary steelmaking, the enhancement of the reaction rate in the low carbon period during the decarburization of steel is considered the most effective method to produce ultralow carbon steel. In a previous study, it was revealed that the surface reaction is dominant during the final stage of the actual refining process. In order to improve the surface reaction rate, it is necessary to enlarge the reaction region, which is usually achieved by increasing the plume eye area. In this study, water model experiments were carried out to estimate the influence of bottom stirring conditions on the gas-liquid reaction rate; for this purpose, the deoxidation rate during the bottom bubbling process was measured. Five types of nozzle configurations were used to study the effect of the plume eye area on the reaction rate at various gas flow rates. The results reveal that the surface reaction rate is influenced by the gas flow rate and the plume eye area. An empirical correlation was developed for the reaction rate and the plume eye area. This correlation was applied to estimate the gas-liquid reaction rate mat the bath surface.

A New Threshold Voltage Model for Omega Gate Cylindrical Nanowire Transistor

In this work, for the first time, we present a physically based analytical threshold voltage model for omega gate silicon nanowire transistor. This model is developed for long channel cylindrical body structure. The potential distribution at each and every point of the of the wire is derived with a closed form solution of two dimensional Poisson's equation, which is then used to model the threshold voltage. Proposed model can be treated as a generalized model, which is valid for both surround gate and semi-surround gate cylindrical transistors. The accuracy of proposed model is verified for different device geometry against the results obtained from three dimensional numerical device simulators and close agreement is observed.

A Computationally Efficient Generalized Poisson Solution for Independent Double-Gate Transistors

Previous techniques used for solving the 1-D Poisson equation ( PE) rigorously for long-channel asymmetric and independent double-gate (IDG) transistors result in potential models that involve multiple intercoupled implicit equations. As these equations need to be solved self-consistently, such potential models are clearly inefficient for compact modeling. This paper reports a different rigorous technique for solving the same PE by which one can obtain the potential profile of a generalized IDG transistor that involves a single implicit equation. The proposed Poisson solution is shown to be computationally more efficient for circuit simulation than the previous solutions.

Identifying N60D mutation in omega subunit of Escherichia coli RNA polymerase by bottom-up proteomic approach

Escherichia coli RNA polymerase is a multi-subunit enzyme containing alpha(2)beta beta'omega sigma, which transcribes DNA template to intermediate RNA product in a sequence specific manner. Although most of the subunits are essential for its function, the smallest subunit omega (average molecular mass similar to 10,105 Da) can be deleted without affecting bacterial growth. Creating a mutant of the omega subunit can aid in improving the understanding of its role. Sequencing of rpoZ gene that codes for omega subunit from a mutant variant suggested a substitution mutation at position 60 of the protein: asparagine (N) -> aspartic acid (D). This mutation was verified at the protein level by following a typical mass spectrometry (MS) based bottom-up proteomic approach. Characterization of in-gel trypsin digested samples by reverse phase liquid chromatography (LC) coupled to electrospray ionization (ESI)-tandem mass spectrometry (MS/MS) enabled in ascertaining this mutation. Electron transfer dissociation (ETD) of triply charged (M + 3H)(3+)] tryptic peptides (residues 53-67]), EIEEGLINNQILDVR from wild-type and EIEEGLIDNQILDVR from mutant, facilitated in unambiguously determining the site of mutation at residue 60.

A Compact Model incorporating Quantum Effects for Ultra-Thin-Body Double-Gate MOSFETs

We propose a compact model which predicts the channel charge density and the drain current which match quite closely with the numerical solution obtained from the Full-Band structure approach. We show that, with this compact model, the channel charge density can be predicted by taking the capacitance based on the physical oxide thickness, as opposed to C-eff, which needs to be taken when using the classical solution.

Effect of a linear potential variation on the gate of an FET

This correspondence aims at reporting the results of an analysis carried out to find the effect of a linear potential variation on the gate of an FET.

Analytical modeling of quantum threshold voltage for triple gate MOSFET

In this work a physically based analytical quantum threshold voltage model for the triple gate long channel metal oxide semiconductor field effect transistor is developed The proposed model is based on the analytical solution of two-dimensional Poisson and two-dimensional Schrodinger equation Proposed model is extended for short channel devices by including semi-empirical correction The impact of effective mass variation with film thicknesses is also discussed using the proposed model All models are fully validated against the professional numerical device simulator for a wide range of device geometries (C) 2010 Elsevier Ltd All rights reserved