A Circuit-Based Proof of Toda′s Theorem

We present a simple proof of Toda′s result (Toda (1989), in "Proceedings, 30th Annual IEEE Symposium on Foundations of Computer Science," pp. 514-519), which states that circled plus P is hard for the Polynomial Hierarchy under randomized reductions. Our approach is circuit-based in the sense that we start with uniform circuit definitions of the Polynomial Hierarchy and apply the Valiant-Vazirani lemma on these circuits (Valiant and Vazirani (1986), Thoeret. Comput. Sci.47, 85-93).

A novel laser direct write technique for fabrication of thin film MICs

A technique for fabrication of thin-film circuits for microwave integrated circuit (MIC) application is presented. This low-cost fabrication technique utilizes laser direct write of copper patterns on alumina substrates. The method obviates the need for photomasks and photolithography. The film deposition mechanism, deposit film analysis, and MIC fabrication sequence are presented. Performance evaluation of MICs fabricated using this technique is also included

A Simple Programmable 2-Pulse Generator for Pulsed NMR NQR Applications

Programmable pulse generator (PPG) circuits using programmable interval timer chips are normally based on a PC or a microprocessor. We describe here a simple low cost programmable two-pulse generator using Intel 8253s in a stand-alone mode, eliminating the need for a PC or a microprocessor, though our design also can be operated via a PC or a microprocessor.

Laser patterning system for integrated optics and storage applications

A computer-controlled laser writing system for optical integrated circuits and data storage is described. The system is characterized by holographic (649F) and high-resolution plates. A minimum linewidth of 2.5 mum is obtained by controlling the system parameters. We show that this system can also be used for data storage applications.

A study of the synthetic methods and properties of graphenes

Graphenes with varying number of layers can be synthesized by using different strategies. Thus, single-layer graphene is prepared by micromechanical cleavage, reduction of single-layer graphene oxide, chemical vapor deposition and other methods. Few-layer graphenes are synthesized by conversion of nanodiamond, arc discharge of graphite and other methods. In this article, we briefly overview the various synthetic methods and the surface, magnetic and electrical properties of the produced graphenes. Few-layer graphenes exhibit ferromagnetic features along with antiferromagnetic properties, independent of the method of preparation. Aside from the data on electrical conductivity of graphenes and graphene-polymer composites, we also present the field-effect transistor characteristics of graphenes. Only single-layer reduced graphene oxide exhibits ambipolar properties. The interaction of electron donor and acceptor molecules with few-layer graphene samples is examined in detail.

Memory Bandwidth and Power Reduction Using Lossy Reference Frame Compression in Video Encoding

Large external memory bandwidth requirement leads to increased system power dissipation and cost in video coding application. Majority of the external memory traffic in video encoder is due to reference data accesses. We describe a lossy reference frame compression technique that can be used in video coding with minimal impact on quality while significantly reducing power and bandwidth requirement. The low cost transformless compression technique uses lossy reference for motion estimation to reduce memory traffic, and lossless reference for motion compensation (MC) to avoid drift. Thus, it is compatible with all existing video standards. We calculate the quantization error bound and show that by storing quantization error separately, bandwidth overhead due to MC can be reduced significantly. The technique meets key requirements specific to the video encode application. 24-39% reduction in peak bandwidth and 23-31% reduction in total average power consumption are observed for IBBP sequences.

Indian Nanoelectronics Users Program An Outreach Vehicle to Expedite Nanoelectronics Research in India

The worldwide research in nanoelectronics is motivated by the fact that scaling of MOSFETs by conventional top down approach will not continue for ever due to fundamental limits imposed by physics even if it is delayed for some more years. The research community in this domain has largely become multidisciplinary trying to discover novel transistor structures built with novel materials so that semiconductor industry can continue to follow its projected roadmap. However, setting up and running a nanoelectronics facility for research is hugely expensive. Therefore it is a common model to setup a central networked facility that can be shared with large number of users across the research community. The Centres for Excellence in Nanoelectronics (CEN) at Indian Institute of Science, Bangalore (IISc) and Indian Institute of Technology, Bombay (IITB) are such central networked facilities setup with funding of about USD 20 million from the Department of Information Technology (DIT), Ministry of Communications and Information Technology (MCIT), Government of India, in 2005. Indian Nanoelectronics Users Program (INUP) is a missionary program not only to spread awareness and provide training in nanoelectronics but also to provide easy access to the latest facilities at CEN in IISc and at IITB for the wider nanoelectronics research community in India. This program, also funded by MCIT, aims to train researchers by conducting workshops, hands-on training programs, and providing access to CEN facilities. This is a unique program aiming to expedite nanoelectronics research in the country, as the funding for projects required for projects proposed by researchers from around India has prior financial approval from the government and requires only technical approval by the IISc/ IITB team. This paper discusses the objectives of INUP, gives brief descriptions of CEN facilities, the training programs conducted by INUP and list various research activities currently under way in the program.

Test Application Time Minimization for RAS using Basis Optimization of Column Decoder

Random Access Scan, which addresses individual flip-flops in a design using a memory array like row and column decoder architecture, has recently attracted widespread attention, due to its potential for lower test application time, test data volume and test power dissipation when compared to traditional Serial Scan. This is because typically only a very limited number of random ``care'' bits in a test response need be modified to create the next test vector. Unlike traditional scan, most flip-flops need not be updated. Test application efficiency can be further improved by organizing the access by word instead of by bit. In this paper we present a new decoder structure that takes advantage of basis vectors and linear algebra to further significantly optimize test application in RAS by performing the write operations on multiple bits consecutively. Simulations performed on benchmark circuits show an average of 2-3 times speed up in test write time compared to conventional RAS.

Probing Single and Bilayer Graphene Field Effect Transistors By Raman Spectroscopy

This article is a review of our work related to Raman studies of single layer and bilayer graphenes as a function Fermi level shift achieved by electrochemically top gating a field effect transistor. Combining the transport and in situ Raman studies of the field effect devices, a quantitative understanding is obtained of the phonon renormalization due to doping of graphene. Results are discussed in the light of time dependent perturbation theory, with electron phonon coupling parameter as an input from the density functional theory. It is seen that phonons near and Gamma and K points of the Brillouin zone are renormalized very differently by doping. Further, Gamma-phonon renormalization is different in bilayer graphene as compared to single layer, originating from their different electronic band structures near the zone boundary K-point. Thus Raman spectroscopy is not only a powerful probe to characterize the number of layers and their quality in a graphene sample, but also to quantitatively evaluate electron phonon coupling required to understand the performance of graphene devices.

High On-Off Ratio Bilayer Graphene Complementary Field Effect Transistors

In this paper, we propose a novel S/D engineering for dual-gated Bilayer Graphene (BLG) Field Effect Transistor (FET) using doped semiconductors (with a bandgap) as source and drain to obtain unipolar complementary transistors. To simulate the device, a self-consistent Non-Equilibrium Green's Function (NEGF) solver has been developed and validated against published experimental data. Using the simulator, we predict an on-off ratio in excess of 10(4) and a subthreshold slope of similar to 110mV/decade with excellent scalability and current saturation, for a 20nm gate length unipolar BLG FET. However, the performance of the proposed device is found to be strongly dependent on the S/D series resistance effect. The obtained results show significant improvements over existing reports, marking an important step towards bilayer graphene logic devices.

Hierarchies of circuit classes that are closed under complement

We examine three hierarchies of circuit classes and show they are closed under complementation. (1) The class of languages recognized by a family of polynomial size skew circuits with width O(w), are closed under complement. (2) The class of languages recognized by family of polynomial size circuits with width O(w) and polynomial tree-size, are closed under complement. (3) The class of languages recognized by a family of polynomial size, O(log(n)) depth, bounded AND fan-in with OR fan-in f (f⩾log(n)) circuits are closed under complement. These improve upon the results of (i) Immerman (1988) and Szelepcsenyi (1988), who show that 𝒩L𝒪𝒢 is closed under complementation, and (ii) Borodin et al. (1989), who show that L𝒪𝒢𝒞ℱL is closed under complement

On generating optimal signal probabilities for random tests: A genetic approach

Genetic Algorithms are robust search and optimization techniques. A Genetic Algorithm based approach for determining the optimal input distributions for generating random test vectors is proposed in the paper. A cost function based on the COP testability measure for determining the efficacy of the input distributions is discussed, A brief overview of Genetic Algorithms (GAs) and the specific details of our implementation are described. Experimental results based on ISCAS-85 benchmark circuits are presented. The performance pf our GA-based approach is compared with previous results. While the GA generates more efficient input distributions than the previous methods which are based on gradient descent search, the overheads of the GA in computing the input distributions are larger. To account for the relatively quick convergence of the gradient descent methods, we analyze the landscape of the COP-based cost function. We prove that the cost function is unimodal in the search space. This feature makes the cost function amenable to optimization by gradient-descent techniques as compared to random search methods such as Genetic Algorithms.

Link failure detection for maintaining session continuity in packet data networks

A link failure in the path of a virtual circuit in a packet data network will lead to premature disconnection of the circuit by the end-points. A soft failure will result in degraded throughput over the virtual circuit. If these failures can be detected quickly and reliably, then appropriate rerouteing strategies can automatically reroute the virtual circuits that use the failed facility. In this paper, we develop a methodology for analysing and designing failure detection schemes for digital facilities. Based on errored second data, we develop a Markov model for the error and failure behaviour of a T1 trunk. The performance of a detection scheme is characterized by its false alarm probability and the detection delay. Using the Markov model, we analyse the performance of detection schemes that use physical layer or link layer information. The schemes basically rely upon detecting the occurrence of severely errored seconds (SESs). A failure is declared when a counter, that is driven by the occurrence of SESs, reaches a certain threshold.For hard failures, the design problem reduces to a proper choice;of the threshold at which failure is declared, and on the connection reattempt parameters of the virtual circuit end-point session recovery procedures. For soft failures, the performance of a detection scheme depends, in addition, on how long and how frequent the error bursts are in a given failure mode. We also propose and analyse a novel Level 2 detection scheme that relies only upon anomalies observable at Level 2, i.e. CRC failures and idle-fill flag errors. Our results suggest that Level 2 schemes that perform as well as Level 1 schemes are possible.

Petri net-based modeling of a class of complex digital systems

We present through the use of Petri Nets, modeling techniques for digital systems realizable using FPGAs. These Petri Net models are used for logic validation at the logic design phase. The technique is illustrated by modeling practical circuits. Further, the utility of the technique with respect to timing analysis of the modeled digital systems is considered. Copyright (C) 1997 Elsevier Science Ltd

Analysis, Design, Modeling, and Implementation of an Active Clamp HF Link Converter

This paper deals with the system oriented analysis, design, modeling, and implementation of active clamp HF link three phase converter. The main advantage of the topology is reduced size, weight, and cost of the isolation transformer. However, violation of basic power conversion rules due to presence of the leakage inductance in the HF transformer causes over voltage stresses across the cycloconverter devices. It makes use of the snubber circuit necessary in such topologies. The conventional RCD snubbers are dissipative in nature and hence inefficient. The efficiency of the system is greatly improved by using regenerative snubber or active clamp circuit. It consists of an active switching device with an anti-parallel diode and one capacitor to absorb the energy stored in the leakage inductance of the isolation transformer and to regenerate the same without affecting circuit performance. The turn on instant and duration of the active device are selected such that it requires simple commutation requirements. The time domain expressions for circuit dynamics, design criteria of the snubber capacitor with two conflicting constrains (over voltage stress across the devices and the resonating current duration), the simulation results based on generalized circuit model and the experimental results based on laboratory prototype are presented.