Effects of Parasitics and Interface Traps on Ballistic Nanowire FET in the Ultimate Quantum Capacitance Limit

In this paper, we focus on the performance of a nanowire field-effect transistor in the ultimate quantum capacitance limit (UQCL) (where only one subband is occupied) in the presence of interface traps (D-it), parasitic capacitance (C-L), and source/drain series resistance (R-s,R-d), using a ballistic transport model and compare the performance with its classical capacitance limit (CCL) counterpart. We discuss four different aspects relevant to the present scenario, namely: 1) gate capacitance; 2) drain-current saturation; 3) subthreshold slope; and 4) scaling performance. To gain physical insights into these effects, we also develop a set of semianalytical equations. The key observations are as follows: 1) A strongly energy-quantized nanowire shows nonmonotonic multiple-peak C-V characteristics due to discrete contributions from individual subbands; 2) the ballistic drain current saturates better in the UQCL than in the CCL, both in the presence and absence of D-it and R-s,R-d; 3) the subthreshold slope does not suffer any relative degradation in the UQCL compared to the CCL, even with Dit and R-s,R-d; 4) the UQCL scaling outperforms the CCL in the ideal condition; and 5) the UQCL scaling is more immune to R-s,R-d, but the presence of D-it and C-L significantly degrades the scaling advantages in the UQCL.

High Starting Torque Drive For Step Motors

A bi-level voltage drive circuit for step motors that can provide the required high starting torque is described. In this circuit, microprocessor 8085 and parallel port interface 8255 are used for generating the code sequence. The inverter buffer 74LS06 provides enough drive to a darlington pair transistor. The comparator LM339 is used to compare the required voltage for step motor with the set value. This circuit can be effectively used for step motors having maximum rated current of less than 15 A with proper heat sink.

Analytical modeling of quantum threshold voltage for triple gate MOSFET

In this work a physically based analytical quantum threshold voltage model for the triple gate long channel metal oxide semiconductor field effect transistor is developed The proposed model is based on the analytical solution of two-dimensional Poisson and two-dimensional Schrodinger equation Proposed model is extended for short channel devices by including semi-empirical correction The impact of effective mass variation with film thicknesses is also discussed using the proposed model All models are fully validated against the professional numerical device simulator for a wide range of device geometries (C) 2010 Elsevier Ltd All rights reserved

Adaptive Keeper Design for Dynamic Logic Circuits Using Rate Sensing Technique

The increasing variability in device leakage has made the design of keepers for wide OR structures a challenging task. The conventional feedback keepers (CONV) can no longer improve the performance of wide dynamic gates for the future technologies. In this paper, we propose an adaptive keeper technique called rate sensing keeper (RSK) that enables faster switching and tracks the variation across different process corners. It can switch upto 1.9x faster (for 20 legs) than CONV and can scale upto 32 legs as against 20 legs for CONV in a 130-nm 1.2-V process. The delay tracking is within 8% across the different process corners. We demonstrate the circuit operation of RSK using a 32 x 8 register file implemented in an industrial 130-nm 1.2-V CMOS process. The performance of individual dynamic logic gates are also evaluated on chip for various keeper techniques. We show that the RSK technique gives superior performance compared to the other alternatives such as Conditional Keeper (CKP) and current mirror-based keeper (LCR).

V-CE Sensing for IGBT Protection in NPC Three Level Converters-Causes For Spurious Trippings and Their Elimination

Neutral point clamped (NPC), three level converters with insulated gate bipolar transistor devices are very popular in medium voltage, high power applications. DC bus short circuit protection is usually done, using the sensed voltage across collector and emitter (i.e., V-CE sensing), of all the devices in a leg. This feature is accommodated with the conventional gate drive circuits used in the two level converters. The similar gate drive circuit, when adopted for NPC three level converter protection, leads to false V-CE fault signals for inner devices of the leg. The paper explains the detailed circuit behavior and reasons, which result in the occurrence of such false V-CE fault signals. This paper also illustrates that such a phenomenon shows dependence on the power factor of the supplied three-phase load. Finally, experimental results are presented to support the analysis. It is shown that the problem can be avoided by blocking out the V-CE sense fault signals of the inner devices of the leg.

Energy-Efficient Fault Tolerance in Chip Multiprocessors Using Critical Value Forwarding

Relentless CMOS scaling coupled with lower design tolerances is making ICs increasingly susceptible to wear-out related permanent faults and transient faults, necessitating on-chip fault tolerance in future chip microprocessors (CMPs). In this paper we introduce a new energy-efficient fault-tolerant CMP architecture known as Redundant Execution using Critical Value Forwarding (RECVF). RECVF is based on two observations: (i) forwarding critical instruction results from the leading to the trailing core enables the latter to execute faster, and (ii) this speedup can be exploited to reduce energy consumption by operating the trailing core at a lower voltage-frequency level. Our evaluation shows that RECVF consumes 37% less energy than conventional dual modular redundant (DMR) execution of a program. It consumes only 1.26 times the energy of a non-fault-tolerant baseline and has a performance overhead of just 1.2%.

A study of the synthetic methods and properties of graphenes

Graphenes with varying number of layers can be synthesized by using different strategies. Thus, single-layer graphene is prepared by micromechanical cleavage, reduction of single-layer graphene oxide, chemical vapor deposition and other methods. Few-layer graphenes are synthesized by conversion of nanodiamond, arc discharge of graphite and other methods. In this article, we briefly overview the various synthetic methods and the surface, magnetic and electrical properties of the produced graphenes. Few-layer graphenes exhibit ferromagnetic features along with antiferromagnetic properties, independent of the method of preparation. Aside from the data on electrical conductivity of graphenes and graphene-polymer composites, we also present the field-effect transistor characteristics of graphenes. Only single-layer reduced graphene oxide exhibits ambipolar properties. The interaction of electron donor and acceptor molecules with few-layer graphene samples is examined in detail.

Indian Nanoelectronics Users Program An Outreach Vehicle to Expedite Nanoelectronics Research in India

The worldwide research in nanoelectronics is motivated by the fact that scaling of MOSFETs by conventional top down approach will not continue for ever due to fundamental limits imposed by physics even if it is delayed for some more years. The research community in this domain has largely become multidisciplinary trying to discover novel transistor structures built with novel materials so that semiconductor industry can continue to follow its projected roadmap. However, setting up and running a nanoelectronics facility for research is hugely expensive. Therefore it is a common model to setup a central networked facility that can be shared with large number of users across the research community. The Centres for Excellence in Nanoelectronics (CEN) at Indian Institute of Science, Bangalore (IISc) and Indian Institute of Technology, Bombay (IITB) are such central networked facilities setup with funding of about USD 20 million from the Department of Information Technology (DIT), Ministry of Communications and Information Technology (MCIT), Government of India, in 2005. Indian Nanoelectronics Users Program (INUP) is a missionary program not only to spread awareness and provide training in nanoelectronics but also to provide easy access to the latest facilities at CEN in IISc and at IITB for the wider nanoelectronics research community in India. This program, also funded by MCIT, aims to train researchers by conducting workshops, hands-on training programs, and providing access to CEN facilities. This is a unique program aiming to expedite nanoelectronics research in the country, as the funding for projects required for projects proposed by researchers from around India has prior financial approval from the government and requires only technical approval by the IISc/ IITB team. This paper discusses the objectives of INUP, gives brief descriptions of CEN facilities, the training programs conducted by INUP and list various research activities currently under way in the program.

Probing Single and Bilayer Graphene Field Effect Transistors By Raman Spectroscopy

This article is a review of our work related to Raman studies of single layer and bilayer graphenes as a function Fermi level shift achieved by electrochemically top gating a field effect transistor. Combining the transport and in situ Raman studies of the field effect devices, a quantitative understanding is obtained of the phonon renormalization due to doping of graphene. Results are discussed in the light of time dependent perturbation theory, with electron phonon coupling parameter as an input from the density functional theory. It is seen that phonons near and Gamma and K points of the Brillouin zone are renormalized very differently by doping. Further, Gamma-phonon renormalization is different in bilayer graphene as compared to single layer, originating from their different electronic band structures near the zone boundary K-point. Thus Raman spectroscopy is not only a powerful probe to characterize the number of layers and their quality in a graphene sample, but also to quantitatively evaluate electron phonon coupling required to understand the performance of graphene devices.

High On-Off Ratio Bilayer Graphene Complementary Field Effect Transistors

In this paper, we propose a novel S/D engineering for dual-gated Bilayer Graphene (BLG) Field Effect Transistor (FET) using doped semiconductors (with a bandgap) as source and drain to obtain unipolar complementary transistors. To simulate the device, a self-consistent Non-Equilibrium Green's Function (NEGF) solver has been developed and validated against published experimental data. Using the simulator, we predict an on-off ratio in excess of 10(4) and a subthreshold slope of similar to 110mV/decade with excellent scalability and current saturation, for a 20nm gate length unipolar BLG FET. However, the performance of the proposed device is found to be strongly dependent on the S/D series resistance effect. The obtained results show significant improvements over existing reports, marking an important step towards bilayer graphene logic devices.

Effect of Post-Metallization Hydrogen Annealing on C-V Characteristic of Zirconia Grown Using Atomic Layer Deposition

Substantial amount of fixed charge present in most of the alternative gate dielectrics gives rise to large shifts in the flat-band voltage (VFB) and charge trapping and de-trapping causes hysterectic changes on voltage cycling. Both phenomena affect stable and reliable transistor operation. In this paper we have studied for the first time the effect of post-metallization hydrogen annealing on the C-V curve of MOS capacitors employing zirconia, one of the most promising gate dielectric. Samples were annealed in hydrogen ambient for up to 30 minutes at different temperatures ranging from room temperature to 400°C. C-V measurements were done after annealing at each temperature and the hysteresis width was calculated from the C-V curves. A minimum hysteresis width of ∼35 mV was observed on annealing the sample at 200°C confirming the excellent suitability of this dielectric

MFIS and MFS structures using SrBi2Ta2O9 thin films for the FRAM applications

Recently there is an increasing demand and extensive research on high density memories, in particular to the ferroelectric random access memory composed of 1T/1C (1 transistor/1 capacitor) or 2T/2C. FRAM's exhibit fast random acess in read/write mode, non - volatility and low power for good performance. An integration of the ferroelectric on Si is the key importance and in this regard, there had been various models proposed like MFS, MFIS, MFMIS structure etc., Choosing the proper insulator is very essential for the better performance of the device and to exhibit excellent electrical characteristics. ZrTiO4 is a potential candidate because of its excellent thermal stability and lattice match on the Si substrate. SrBi2Ta2O9 and ZrTiO4 thin films were prepared on p - type Si substrate by pulsed excimer laser ablation technique. Optimization of both ZT and SBT thin films in MFS and MFIS structure had been done based on the annealing, oxygen partial pressures and substrate temperatures to have proper texture of the thin films. The dc leakage current, P - E hysteresis, capacitance - voltage and conductance - voltage measurement were carried out. The effect of the frequency dependence on MFIS structure was observed in the C – V curve. It displays a transition of C - V curve from high frequency to low frequency curve on subjection to varied frequencies. Density of interface states has been calculated using Terman and high - low frequency C - V curve. The effect of memory window in the C - V hysteresis were analysed in terms of film thickness and annealing temperatures. DC conduction mechanism were analysed in terms of poole - frenkel, Schottky and space charge limited conduction separately on MFS, MIS structure.

MFIS and MFS structures using SrBi2Ta2O9 thin films for the FRAM applications

Recently there is an increasing demand and extensive research on high density memories, in particular to the ferroelectric random access memory composed of 1T/1C (1 transistor/1 capacitor) or 2T/2C. FRAM's exhibit fast random acess in read/write mode, non - volatility and low power for good performance. An integration of the ferroelectric on Si is the key importance and in this regard, there had been various models proposed like MFS, MFIS, MFMIS structure etc., Choosing the proper insulator is very essential for the better performance of the device and to exhibit excellent electrical characteristics. ZrTiO4 is a potential candidate because of its excellent thermal stability and lattice match on the Si substrate. SrBi2Ta2O9 and ZrTiO4 thin films were prepared on p - type Si substrate by pulsed excimer laser ablation technique. Optimization of both ZT and SBT thin films in MFS and MFIS structure had been done based on the annealing, oxygen partial pressures and substrate temperatures to have proper texture of the thin films. The dc leakage current, P - E hysteresis, capacitance - voltage and conductance - voltage measurement were carried out. The effect of the frequency dependence on MFIS structure was observed in the C – V curve. It displays a transition of C - V curve from high frequency to low frequency curve on subjection to varied frequencies. Density of interface states has been calculated using Terman and high - low frequency C - V curve. The effect of memory window in the C - V hysteresis were analysed in terms of film thickness and annealing temperatures. DC conduction mechanism were analysed in terms of poole - frenkel, Schottky and space charge limited conduction separately on MFS, MIS structure.

A Novel VSI- and CSI-Fed Dual Stator Induction Motor Drive Topology for Medium-Voltage Drive Applications

A new configuration is proposed for high-power induction motor drives. The induction machine is provided with two three-phase stator windings with their axes in line. One winding is designed for higher voltage and is meant to handle the main (active) power. The second winding is designed for lower voltage and is meant to carry the excitation (reactive) power. The excitation winding is powered by an insulated-gate-bipolar-transistor-based voltage source inverter with an output filter. The power winding is fed by a load-commutated current source inverter. The commutation of thyristors in the load-commutated inverter (LCI) is achieved by injecting the required leading reactive power from the excitation inverter. The MMF harmonics due to the LCI current are also cancelled out by injecting a suitable compensating component from the excitation inverter, so that the electromagnetic torque of the machine is smooth. Results from a prototype drive are presented to demonstrate the concept.

A low power, process invariant keeper design for high speed dynamic logic circuits

A low power keeper circuit using the concept of rate sensing has been proposed. The proposed technique reduces the amount of short circuit power dissipation in the domino gate by 70% compared to the conventional keeper technique. Also the total power-delay product is 26% lower compared to the previously reported techniques. The process tracking capability of the design enables the domino gate to achieve uniform delay across different process corners. This reduces the amount of short circuit power dissipation that occurs in the cascaded domino gates by 90%. The use of the proposed technique in the read path of a register file reduces the energy requirement by 26% as compared to the other keeper techniques. The proposed technique has been prototyped in 130nm CMOS technology.