Behaviour of power MOSFETs at cryogenic temperatures

In this paper an investigation is reported on Siemens-power-metal-oxide-semiconductor (SIPMOS) transistors of both p and n channel types, for their suitability for cryogenic applications. The drain characteristics, temperature dependence of Rds(on) and switching behaviour have been studied in the temperature range 4.2 – 300 K in BSS91 and BSS92 MOSFETs. The experiments reveal that these types of power transistors are well suited for operations down to ≈ 30 K. However, below 30 K the operating characteristics make them unsuitable for application. This arises because of carrier freeze-out in the n− region on the substrate, which forms a drain.

Field-tunable stochasticity in the magnetization reversal of a cylindrical nanomagnet

The nature of magnetization reversal in an isolated cylindrical nanomagnet has been studied employing time-resolved magnetoresistance measurement. We find that the reversal mode is highly stochastic, occurring either by multimode or single-step switching. Intriguingly, the stochasticity was found to depend on the alignment of the driving magnetic field to the long axis of the nanowires, where predominantly multimode switching gives way to single-step switching behavior as the field direction is rotated from parallel to transverse with respect to the nanowire axis.

Large-Signal Model for Independent DG MOSFET

In this paper, we show the limitations of the traditional charge linearization techniques for modeling terminal charges of the independent double-gate metal-oxide-semiconductor field-effect transistors. Based on our recent computationally efficient Poisson solution for independent double gate transistors, we propose a new charge linearization technique to model the terminal charges and transcapacitances. We report two different types of quasistatic large-signal models for the long-channel device. In the first type, the terminal charges are expressed as closed-form functions of the source- and drain-end inversion charge densities and found to be accurate when the potential distribution at source end of the channel is hyperbolic in nature. The second type, which is found to be accurate in all regimes of operations, is based on the quadratic spline collocation technique and requires the input voltage equation to be solved two more times, apart from the source and drain ends.

Microscopic Mechanism of 1/f Noise in Graphene: Role of Energy Band Dispersion

A distinctive feature of single-layer graphene is the linearly dispersive energy bands, which in the case of multilayer graphene become parabolic. A simple electrical transport-based probe to differentiate between these two band structures will be immensely valuable, particularly when quantum Hall measurements are difficult, such as in chemically synthesized graphene nanoribbons. Here we show that the flicker noise, or the 1/f noise, in electrical resistance is a sensitive and robust probe to the band structure of graphene. At low temperatures, the dependence of noise magnitude on the carrier density was found to be opposite for the linear and parabolic bands. We explain our data with a comprehensive theoretical model that clarifies several puzzling issues concerning the microscopic origin of flicker noise in graphene field-effect transistors (GraFET).

Si, Si-Ge and the new heterostructure world

Semiconductor heterostructures based on AlAs/GaAs and other III-V compounds have been the focus of active research for some time now. Ih the last decade, a new heterostructure material, the strained Si/SiGe system, has emerged. This heterojunction technology can potentially be integrated into the current VLSI environment with large-scale impact in the growing microelectronics market. Si/SiGe heterojunction bipolar transistors with cut-off frequencies exceeding 100 GHz and other electronic and optical devices with superior properties compared to all-Si technology have been demonstrated in laboratories worldwide.

Electrical and Optical Properties of Diketopyrrolopyrrole-Based Copolymer Interfaces in Thin Film Devices

Two donor acceptor diketopyrrolopyrrole (DPP)-based copolymers (PDPP-BBT and TDPP-BBT) have been synthesized for their application in organic devices such as metal-insulator semiconductor (MIS) diodes and field-effect transistors (FETs). The semiconductor-dielectric interface was characterized by capacitance-voltage and conductance-voltage methods. These measurements yield an interface trap density of 4.2 x 10(12) eV(-1) cm(-2) in TDPP-BBT and 3.5 x 10(12) eV(-1) cm(-2) in PDPP-BBT at the flat-band voltage. The FETs based on these spincoated DPP copolymers display p-channel behavior with hole mobilities of the order 10(-3) cm(2)/(V s). Light scattering studies from PDPP-BBT FETs show almost no change in the Raman spectrum after the devices are allowed to operate at a gate voltage, indicating that the FETs suffer minimal damage due to the metal-polymer contact or the application of an electric field. As a comparison Raman intensity profile from the channel-Au contact layer in pentacene FETs are presented, which show a distinct change before and after biasing.

Universal Stability and Temperature Dependent Phase Transformation in Group VIIIB-IB Transition Metal FCC Nanowires

Atomistic simulation of Ag, Al, Au, Cu, Ni, Pd, and Pt FCC metallic nanowires show a universal FCC -> HCP phase transformation below a critical cross-sectional size, which is reported for the first time in this paper. The newly observed HCP structure is also confirmed from previous experimental results. Above the critical cross-sectional size, initial < 100 >/{100} FCC metallic nanowires are found to be metastable. External thermal heating shows the transformation of metastable < 100 >/{100} FCC nanowires into < 110 >/{111} stable configuration. Size dependent metastability/instability is also correlated with initial residual stresses of the nanowire by use of molecular static simulation using the conjugant gradient method at a temperature of 0 K. It is found that a smaller cross-sectional dimension of an initial FCC nanowire shows instability due to higher initial residual stresses, and the nanowire is transformed into the novel HCP structure. The initial residual stress shows reduction with an increase in the cross-sectional size of the nanowires. A size dependent critical temperature is also reported for metastable FCC nanowires using molecular dynamic, to capture the < 110 >/{111} to < 100 >/{100} shape memory and pseudoelasticity.

Synthesis and Self-Assembly of Donor-Acceptor-Donor Based Oligothiophenes and Their Optoelectronic Properties

In this work, the synthesis of an oligothiophene having a donor acceptor donor (D-A-D) chromophore with hydrogen bonding groups is described. The D-A-D molecule was demonstrated to self-organize via intermolecular H-bonding between barbituric acid units. Interactions between the oligothiophene subunits were also found to be important, affording nanoribbons that could be observed by atomic force and transmission electron microscopy. The applicability of the oligothiophene for organic electronic applications was investigated by fabricating organic field-effect transistors (OFETs) and organic photovoltaic devices. The OFET measurements yielded p-type mobility of 7 x 10(-7) cm(2)/(Vs), and when blended with C(60)-PCBM, the photovoltaic efficiency was observed to be 0.18%.

Tailoring of Structural Morphology of Silver Nanowires in Electrochemical Growth

Noble metal such as Ag normally exists in an fcc crystal structure. However as the size of the material is decreased to nanometer lengthscales, a structural transformation from that of its bulk state can be expected with new atomic arrangements due to competition between internal packing and minimization of surface energy. In many previous studies, it has been shown that silver nanowires (AGNWs) grown inside anodic alumina (AAO) templates by ac or dc electrochemical deposition from silver salts or complexes, adopt fcc structure and below some critical diameter ∼ 20 nm they may acquire hcp structure at low temperature. This is, however, critically dependant on the nature of confinement, as AgNWs grown inside nanotube confinement with subnanometer diameter have been reported to have fcc structure. Hence the question of the crystal structure of metal nanowires under combined influence of confinement, temperature and deposition condition remains open. In this abstract we show that the alternative crystal structures of AGNWs at room temperature can be achieved with electrochemical growth processes under specific conditions determined by the deposition parameters and nature of confinement. We fabricated AgNWs of 4H hexagonal structure with diameters 30 – 80 nm inside polycarbonate (PC) templates with a modified dc electrodeposition technique, where the nanowires were grown at deposition potentials as low as 10 mV in 2 M silver nitrate solution[1]. We call this low-potential electrodeposition (LPED) since the electrodeposition process occurs at potential much less than the standard Nernst potential (770 mV) of silver. Two types of electrodes were used – stainless steel and sputtered thin Pt film, neither of which had any influence on the crystal structure of the nanowires. EDS elemental analysis showed the nanowires to consist only of silver. Although the precise atomic dynamics during the LPED process is unclear at present, we investigated this with HRTEM (high-resolution transmission electron microscopy) characterization of nanowires grown over various deposition times, as well as electrical conductivity measurements. These experiments indicate that nanowire growth does not occur through a three-dimensional diffusion controlled process, as proposed for conventional over-potential deposition, but follow a novel instantaneous linear growth mechanism. Further experiments showed that, (a) conventional electrochemical growth at a small over-potential in a 2 mM AgNO3 solution yields nanowires with expected fcc structure inside the same PC templates, and (2) no nanowire was observed under the LPED conditions inside hard AAO templates, indicating that LPED-growth process, and hcp structure of the corresponding nanowires depend on deposition parameters, as well as nature of confinement.

Unified Vdd Vth Optimization Based DVFM Controller for a Logic Block

In this paper analytical expressions for optimal Vdd and Vth to minimize energy for a given speed constraint are derived. These expressions are based on the EKV model for transistors and are valid in both strong inversion and sub threshold regions. The effect of gate leakage on the optimal Vdd and Vth is analyzed. A new gradient based algorithm for controlling Vdd and Vth based on delay and power monitoring results is proposed. A Vdd-Vth controller which uses the algorithm to dynamically control the supply and threshold voltage of a representative logic block (sum of absolute difference computation of an MPEG decoder) is designed. Simulation results using 65 nm predictive technology models are given.

Generation of Minimum Leakage Input Vectors with Constrained NBTI Degradation

Technology scaling has caused Negative Bias Temperature Instability (NBTI) to emerge as a major circuit reliability concern. Simultaneously leakage power is becoming a greater fraction of the total power dissipated by logic circuits. As both NBTI and leakage power are highly dependent on vectors applied at the circuit’s inputs, they can be minimized by applying carefully chosen input vectors during periods when the circuit is in standby or idle mode. Unfortunately input vectors that minimize leakage power are not the ones that minimize NBTI degradation, so there is a need for a methodology to generate input vectors that minimize both of these variables.This paper proposes such a systematic methodology for the generation of input vectors which minimize leakage power under the constraint that NBTI degradation does not exceed a specified limit. These input vectors can be applied at the primary inputs of a circuit when it is in standby/idle mode and are such that the gates dissipate only a small amount of leakage power and also allow a large majority of the transistors on critical paths to be in the “recovery” phase of NBTI degradation. The advantage of this methodology is that allowing circuit designers to constrain NBTI degradation to below a specified limit enables tighter guardbanding, increasing performance. Our methodology guarantees that the generated input vector dissipates the least leakage power among all the input vectors that satisfy the degradation constraint. We formulate the problem as a zero-one integer linear program and show that this formulation produces input vectors whose leakage power is within 1% of a minimum leakage vector selected by a search algorithm and simultaneously reduces NBTI by about 5.75% of maximum circuit delay as compared to the worst case NBTI degradation. Our paper also proposes two new algorithms for the identification of circuit paths that are affected the most by NBTI degradation. The number of such paths identified by our algorithms are an order of magnitude fewer than previously proposed heuristics.

Modeling of the Effects of Process Variations on Circuit Delay at 65nm

A novel methodology for modeling the effects of process variations on circuit delay performance is proposed by relating the variations in process parameters to variations in delay metric of a complex digital circuit. The delay of a 2-input NAND gate with 65nm gate length transistors is extensively characterized by mixed-mode simulations which is then used as a library element. The variation in saturation current Ionat the device level, and the variation in rising/falling edge stage delay for the NAND gate at the circuit level, are taken as performance metrics. A 4-bit x 4-bit Wallace tree multiplier circuit is used as a representative combinational circuit to demonstrate the proposed methodology. The variation in the multiplier delay is characterized, to obtain delay distributions, by an extensive Monte Carlo analysis. An analytical model based on CV/I metric is proposed, to extend this methodology for a generic technology library with a variety of library elements.

An Area-Efficient Noise-Adaptive Neural Amplifier in 130 nm CMOS Technology

Chronic recording of neural signals is indispensable in designing efficient brain–machine interfaces and to elucidate human neurophysiology. The advent of multichannel micro-electrode arrays has driven the need for electronics to record neural signals from many neurons. The dynamic range of the system can vary over time due to change in electrode–neuron distance and background noise. We propose a neural amplifier in UMC 130 nm, 1P8M complementary metal–oxide–semiconductor (CMOS) technology. It can be biased adaptively from 200 nA to 2 $mu{rm A}$, modulating input referred noise from 9.92 $mu{rm V}$ to 3.9 $mu{rm V}$. We also describe a low noise design technique which minimizes the noise contribution of the load circuitry. Optimum sizing of the input transistors minimizes the accentuation of the input referred noise of the amplifier and obviates the need of large input capacitance. The amplifier achieves a noise efficiency factor of 2.58. The amplifier can pass signal from 5 Hz to 7 kHz and the bandwidth of the amplifier can be tuned for rejecting low field potentials (LFP) and power line interference. The amplifier achieves a mid-band voltage gain of 37 dB. In vitro experiments are performed to validate the applicability of the neural low noise amplifier in neural recording systems.

Designing copper-zirconium based nanowires for improving yield strength and plasticity by configuring surface atoms

Epitaxial-Bain-Path and Uniaxial-Bain-Path studies reveal that a B2-CuZr nanowire with Zr atoms on the surface is energetically more stable compared to a B2-CuZr nanowire with Cu atoms on the surface. Nanowires of cross-sectional dimensions in the range of similar to 20-50 are considered. Such stability is also correlated with the initial state of stress in the nanowires. It is also demonstrated here that a more stable structure, i.e., B2-CuZr nanowire with Zr atoms at surface shows improved yield strength compared to B2-CuZr nanowire with Cu atoms at surface site, over range of temperature under both the tensile and the compressive loadings. Nearly 18% increase in the average yield strength under tensile loading and nearly 26% increase in the averaged yield strength under compressive loading are observed for nanowires with various cross-sectional dimensions and temperatures. It is also observed that the B2-CuZr nanowire with Cu atom at the surface site shows a decrease in failure/plastic strain with an increase in temperature. On the other hand, B2-CuZr nanowires with Zr at the surface site shows an improvement in failure/plastic strain, specially at higher temperature as compared to the B2-CuZr nanowires which are having Cu atoms at the surface site. Finally, a possible design methodology for an energetically stable nano-structure with improved thermo-mechanical properties via manipulating the surface atom configuration is proposed.

Amorphous Hydrogenated Silicon: A Perspective on Circuit Synthesis

Abstract | Non-crystalline or glassy semiconductors are of great research interest for the fabrication of large area electronic systems such as displays and image sensors. Good uniformity over large areas, low temperature fabrication and the promise of low cost electronics on large area mechanically flexible and rigid substrates are some attractive features of these technologies. The article focusses on amorphous hydrogenated silicon thin film transistors, and reviews the problems, solutions and applications of these devices.